Patents by Inventor Wen Huang

Wen Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190214347
    Abstract: A semiconductor package including a stacked-die structure, a second encapsulant laterally encapsulating the stacked-die structure and a redistribution layer disposed on the second encapsulant and the staked-die structure is provided. The stacked-die structure includes a first semiconductor die including a first active surface, a circuit layer disposed on the first active surface, a second semiconductor die including a second active surface facing towards the first active surface, a plurality of conductive features distributed at the circuit layer and electrically connected to the first and second semiconductor die and a first encapsulant encapsulating the second semiconductor die and the conductive features. A portion of the conductive features surrounds the second semiconductor die. The redistribution layer is electrically connected to the staked-die structure. A manufacturing method of a semiconductor package is also provided.
    Type: Application
    Filed: January 10, 2018
    Publication date: July 11, 2019
    Applicant: Powertech Technology Inc.
    Inventors: Chien-Wen Huang, Chia-Wei Chiang, Wen-Jeng Fan, Li-Chih Fang
  • Patent number: 10349083
    Abstract: A method and apparatus for low-latency illumination compensation in a three-dimensional (3D) and multi-view coding system are disclosed. According to the present invention, the encoder determines whether to enable or disable the illumination compensation for the current picture or slice based on a condition related to statistic associated with a selected reference picture or slice respectively, or related to high-level coding information associated with the current picture or slice respectively. The high-level coding information associated with the current picture or slice excludes any information related to pixel values of the current picture or slice respectively. The illumination compensation is them applied according to the decision made by the encoder. A similar low-latency method is also applied for depth lookup table (DLT) based coding.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: July 9, 2019
    Assignee: HFI INNOVATION INC.
    Inventors: Yi-Wen Chen, Kai Zhang, Jian-Liang Lin, Yu-Wen Huang
  • Publication number: 20190205666
    Abstract: A method is to be implemented by a processor connected to a storage device and an image capturing device, and includes steps of: performing a first and a second classifications on an image received from the image capturing device for respectively obtaining first and second results of obstacle detection, and storing the same in the storage device; determining whether there is a distinct obstacle, which is an obstacle indicated by one of the first and second results of obstacle detection, and not indicated by the other one of the first and second results of obstacle detection; and calculating a penalty score based on the distinct obstacle, and updating a credibility score by subtracting the penalty score therefrom.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Inventors: Chuan-Ren LI, Han-Wen HUANG, Li-You SYU
  • Patent number: 10337206
    Abstract: A hidden-lock door panel for use in a container includes a door panel body, a covering lid, a first lock, and a second lock. The door panel body includes a hidden space. The covering lid is disposed corresponding to the hidden space and slidably connected to the door panel body. The first lock and the second lock are both disposed in the hidden space. The first lock is an electronic lock and is used to control whether the covering lid can be released to slide. The second lock is used to control the door panel body to be unlocked or locked with respect to the container. Accordingly, unknowing persons are prevented from opening or breaking the door lock.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: July 2, 2019
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yen-Wen Huang, Kuan-Lung Wu, Chia-Hui Chen
  • Publication number: 20190194142
    Abstract: The present invention discloses a compound of the formula (I), which acts as an agonist of adenosine monophosphate-activated protein kinase, which induce phosphorylation and activation of AMPK?, thereby further regulating downstream signaling pathways, inhibiting growth and proliferation of liver cancer cells and breast cancer cells, and also inducing apoptosis of adipocytes. Therefore, the compound provided by the present invention can be utilised for treatment and preparation of pharmaceutical composition for cancer, and lipid metabolism-related diseases or syndromes mediated by AMPK.
    Type: Application
    Filed: September 6, 2017
    Publication date: June 27, 2019
    Inventors: Chung-Wai SHIAU, Jung-Chen SU, Yan-Ju LIN, Jui-Wen HUANG
  • Publication number: 20190194137
    Abstract: A compound of formula (I) or a pharmaceutically acceptable salt thereof is provided. In formula (I), Ar is indazole, 5-isoquinoline, 6-isoquinoline, or their N-oxide. X is —C(?Z)—, wherein Z is N—CN, NH, NR4, NCOR4, NCONR4R5, NCO-aryl, S, or O. Y and J are independently H, alkyl, aryl, aminoalkyl, —NH2, —CN, —OH, —O-alkyl, —O-aryl, —COOH, —COOR4, —CONHR4, —CONHCH2-aryl, —CONR4CH2-aryl, —NHCOR4, halogen, halogened alkyl, -alkyl-OR4, -alkyl-ONO2, alkyl-ONO2, —OCOOR4, —O(C?O)-aryl, —CHR4OH, —CH2OH, —CH2O(C?O)-aryl, —CH2O(C?O)—R4, —CHR4O(C?O)-aryl, —CHR4O(C?O)—R4, unsaturated carboxylic ester, substituted alkynyl, —NHSO2R4, —SO2R4, —SO2NHR4, or —SO2NR4R5, or Y and J bond together to form a carbocylic or aromatic ring, wherein R4 and R5 are independently H, substituted C1-C6 alkyl, substituted aryl, cycloalkyl, alkylaryl, -alkyl-NR6R7, —S(O)0-2-(alkyl-NR6R7).
    Type: Application
    Filed: November 30, 2018
    Publication date: June 27, 2019
    Applicant: Industrial Technology Research Institute
    Inventors: Chih-Hung CHEN, Yi-Hsun CHEN, Jui-Wen HUANG, Kuo-Kuei HUANG, Chih-Peng LIU, Chrong-Shiong HWANG
  • Publication number: 20190187279
    Abstract: An ultrasonic diagnostic imaging system and method translates an aperture across an array transducer which is less that the size of the array. At each aperture location a transmit beam is focused above, or alternatively below, the array and a region of interest being scanned from the aperture location, resulting in broad insonification of the region of interest. At the lateral ends of the array the aperture is no longer translated but the focal point of the transmit beam is translated from the same aperture position, preferably with tilting of the beam direction. Multiple receive beams are processed in response to each transmit event and the overlapping receive beams and echo locations are spatially combined to produce synthetic transmit focusing over the center of the image field and noise reduction by spatial compounding at the lateral ends of the image field.
    Type: Application
    Filed: June 12, 2017
    Publication date: June 20, 2019
    Inventors: Jean-Luc Robert, Man Nguyen, Ramon Quido Erkamp, Sheng-Wen Huang, Emil George Radulescu
  • Patent number: 10324604
    Abstract: An electronic device and a method for controlling zooming of a displayed object includes receiving a single-point slide operation performed by a user on a displayed object of a touch screen, generating a slide signal, parsing the slide signal to obtain a slide track and a feature value of the single-point slide operation, determining whether the feature value of at least one point in the single-point slide operation is greater than a preset value, and controlling zooming of the displayed object according to the slide track when the feature value is greater than the preset value. A slide track and a feature value of a single-point slide operation of a user are identified, and zooming of a displayed object of the touch screen is controlled when the feature value is greater than a preset value.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: June 18, 2019
    Assignee: HUAWEI DEVICE CO., LTD.
    Inventors: Wen Huang, Jianchun Zhang
  • Patent number: 10327010
    Abstract: An encoder for receiving a video frame and performing encoding processes to generate an encoded bitstream includes: a fidelity enhancement block, for performing a fidelity enhancement technique on processed data utilizing a partition method, and generating fidelity enhancement information comprising at least one parameter associated with a partition structure, wherein the fidelity enhancement technique comprises applying discrepancy modeling based on DC offset; and an entropy coding block, coupled to the fidelity enhancement block, for encoding the fidelity enhancement information, and embedding the encoded fidelity enhancement information into the encoded bitstream.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: June 18, 2019
    Assignee: HFI Innovation Inc.
    Inventors: Shaw-Min Lei, Yu-Wen Huang, Xun Guo
  • Patent number: 10323237
    Abstract: A lysozyme having improved enzymatic activity is disclosed. The amino acid sequence of the lysozyme is a modified amino acid sequence of SEQ ID NO: 2 or a modified amino acid sequence with at least 80% sequence identity of SEQ ID NO: 2, wherein the modification is a substitution of histidine at position 166 or a corresponding position with lysine.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: June 18, 2019
    Assignee: CHENGDU BEACON BIO-TECHNOLOGY CO., LTD.
    Inventors: Chun-Chi Chen, Tao Wang, Jian-Wen Huang, Rey-Ting Guo
  • Publication number: 20190182057
    Abstract: A power over Ethernet device is provided. The power over Ethernet device includes a first Ethernet connector, an Ethernet transformer circuit, and a detection circuit. The first Ethernet connector is coupled to a second Ethernet connector of a network device via an Ethernet cable and has a first reserve pin and a second reserve pin. The Ethernet transformer circuit is coupled to the first Ethernet connector to provide a supply voltage to the Ethernet cable to transfer the supply voltage to the network device. The detection circuit receives the supply voltage and is coupled to the Ethernet transformer circuit, the first reserve pin, and the second reserve pin to provide a reference voltage to the first reserve pin and receives an identification voltage from the second reserve pin to determine whether the network device is a powered device.
    Type: Application
    Filed: October 16, 2018
    Publication date: June 13, 2019
    Applicant: PEGATRON CORPORATION
    Inventors: Chao-Wen Huang, Yu-Chung Chang, Feng-Liang Lai, Wen-Kai Tai
  • Publication number: 20190182505
    Abstract: Video processing methods and apparatuses for encoding or decoding video data comprise receiving input data associated with a current block in a current picture, determining a first reference block, splitting the current block into multiple partitions according to predicted textures of the first reference block, and separately predicting or compensating each partition of the current block to generate predicted regions or compensated regions. The current block is encoded according to the predicted regions and original data of the current block or the current block is decoded by reconstructing the current block according to the compensated regions of the current block.
    Type: Application
    Filed: August 10, 2017
    Publication date: June 13, 2019
    Inventors: Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG
  • Patent number: 10321141
    Abstract: A method and apparatus for palette coding of a block of video data by initializing the palette or triplet palette or using a selected palette or triplet palette from a preceding image area for the beginning block of the current image area are disclosed. The method receives input data associated with a current image area consisting of multiple blocks. For the beginning block, the palette predictor is determined based on an initial palette or triplet palette or based on a selected palette or triplet palette associated with a selected block located at a location before the end of a preceding image area. For blocks of the current image area, palette coding is applied to the blocks, where at least one block uses the palette predictor for the beginning block as the palette predictor.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: June 11, 2019
    Assignee: HFI INNOVATION INC.
    Inventors: Tzu-Der Chuang, Wang-Lin Lai, Yu-Chen Sun, Shan Liu, Xiaozhong Xu, Yu-Wen Huang, Ding-Yun Chen
  • Patent number: 10321151
    Abstract: A method and apparatus of adaptive interpolation filter for motion compensation with fractional-pixel accuracy are disclosed. Embodiments of the present invention generate interpolated reference samples at non-integer locations based on existing reference samples in a reference block by using an interpolation filter set adaptively according to pixel location and/or pixel characteristics. A current block is then encoded or decoded using a temporal predictor including the interpolated reference samples. The adaptive interpolation filter can be applied to the prediction unit (PU). In one embodiment, the interpolation filter set consists of interpolation filters having different filter lengths. An interpolation filter with a longer tap length is applied to generate interpolated reference samples farther from the block boundary and an interpolation filter with a shorter tap length is applied to generate interpolated reference samples closer to the block boundary.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: June 11, 2019
    Assignee: MEDIATEK INC.
    Inventors: Ching-Yeh Chen, Yu-Wen Huang
  • Publication number: 20190172949
    Abstract: A method of fabricating a fin structure with tensile stress includes providing a structure divided into an N-type transistor region and a P-type transistor region. Next, two first trenches and two second trenches are formed in the substrate. The first trenches define a fin structure. The second trenches segment the first trenches and the fin. Later, a flowable chemical vapor deposition is performed to form a silicon oxide layer filling the first trenches and the second trenches. Then, a patterned mask is formed only within the N-type transistor region. The patterned mask only covers the silicon oxide layer in the second trenches. Subsequently, part of the silicon oxide layer is removed to make the exposed silicon oxide layer lower than the top surface of the fin structure by taking the patterned mask as a mask. Finally, the patterned mask is removed.
    Type: Application
    Filed: January 18, 2019
    Publication date: June 6, 2019
    Inventors: Kai-Lin Lee, Zhi-Cheng Lee, Wei-Jen Chen, Ting-Hsuan Kang, Ren-Yu He, Hung-Wen Huang, Chi-Hsiao Chen, Hao-Hsiang Yang, An-Shih Shih, Chuang-Han Hsieh
  • Publication number: 20190160408
    Abstract: Disclosed is glue-free airtight filtering equipment comprising a filter housing, a plurality of filter elements and a plurality of receiving supporting elements, each filter element having a filtering surface, the plurality of filter elements being detachably disposed in the filtering space in a manner that the filtering surface is parallel to the upper surface and the bottom surface of the filter housing, and the plurality of receiving supporting elements allocating on an inner wall of the filter housing and being spaced apart from each other with a designated distance so as to correspondingly receive and support the plurality of filter elements, wherein a gap is provided between the filter element and the inner wall of the filter housing, and the filtering surface of the filter element and the maximum value of the gap satisfy a relational expression.
    Type: Application
    Filed: October 30, 2018
    Publication date: May 30, 2019
    Applicant: GREENFILTEC TAIWAN LIMITED
    Inventors: Ming-Wen HUANG, Yi-Hui YU
  • Publication number: 20190164844
    Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin on a substrate, a second fin on the substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes an insulating liner and a fill material on the insulating liner. The insulating liner abuts a first sidewall of the first fin and a second sidewall of the second fin. The insulating liner includes a material with a band gap greater than 5 eV.
    Type: Application
    Filed: March 15, 2018
    Publication date: May 30, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wen HUANG, Chia-Hui LIN, Jaming CHANG, Jei Ming CHEN, Kai Hung CHENG
  • Patent number: 10299678
    Abstract: An apparatus for detecting conductance parameter of high protein body fluid sample is provided. The apparatus includes at least one liquid collection element, and at least two electrodes horizontally aligned in the liquid collection element. Also provided are methods for detecting dehydration in a subject, comprising the steps of measuring the conductance parameter of the saliva of the subject.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: May 28, 2019
    Assignees: CHANG GUNG MEMORIAL HOSPITAL, CHIAYI, NATIONAL APPLIED RESEARCH LABORATORIES, NATIONAL TAIWAN UNIVERSITY
    Inventors: Jen-Tsung Yang, Leng-Chieh Lin, I-Neng Lee, Jo-Wen Huang, Jer-Liang Andrew Yeh, Ming-Yu Lin, Yen-Pei Lu, Chih-Ting Lin, Chia-Hong Gao
  • Publication number: 20190157405
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a gate spacer, a source/drain structure, a contact structure, a glue layer and a barrier layer. The gate structure is positioned over a fin structure. The gate spacer is positioned over the fin structure and on a sidewall surface of the gate structure. The source/drain structure is positioned in the fin structure and adjacent to the gate spacer. The contact structure is positioned over the source/drain structure. The glue layer covers a bottom surface and a sidewall surface of the contact structure. The barrier layer encircles the sidewall surface of the contact structure. A bottom surface of the glue layer is exposed to the barrier layer.
    Type: Application
    Filed: May 30, 2018
    Publication date: May 23, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wen HUANG, Chung-Ting KO, Hong-Hsien KE, Chia-Hui LIN, Tai-Chun HUANG
  • Patent number: D852597
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: July 2, 2019
    Inventor: Tsung-Wen Huang