Patents by Inventor Wen-Hung Lo
Wen-Hung Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240402740Abstract: Power supply circuits in which a supplemental current driver is utilized to boost the current provided by a voltage regulator. The supplementing driver detects operating conditions for providing the supplementary current, and may be trained to provide particular amounts of current in response to particular operation conditions of a circuit load.Type: ApplicationFiled: June 1, 2023Publication date: December 5, 2024Applicant: NVIDIA Corp.Inventors: Zhonghua Li, Wen-Hung Lo, Michael Ivan Halfen, Abhishek Dhir, Jaewon Lee, Jiwang Lee, CHUNJEN SU
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Publication number: 20240329083Abstract: A position-adjustable probing device comprises a stationary probe comprising a first coaxial structure having a first needle core, a first dielectric layer, and a first exterior conductive layer, and a first and a second movable probes. The first movable probe arranged at a first side of the stationary probe comprises a ground needle core, and a first extending structure comprising a first planar structure electrically contacted with the stationary probe through a first movement, a first top surface and a first bottom surface. The second movable probe arranged at a second side of the stationary needle comprises a second coaxial structure comprising a second needle core, a second dielectric layer, and a second exterior conductive layer, and a second extending structure comprising a second planar structure electrically contacted with the stationary probe through a second movement, a second top surface, and a second bottom surface.Type: ApplicationFiled: March 1, 2024Publication date: October 3, 2024Inventors: CHIA-NAN CHOU, Chung-Yen Huang, Wen-Chin Yang, Wen-Hung LO, Wei-Lwen Yeh, Chih-Hao Ho
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Publication number: 20240235557Abstract: A multi-rank circuit system includes multiple transmitters each switchably coupled to a first end of a shared input/output (IO) channel and a unified receiver coupled to a second end of the shared IO channel. The unified receiver is coupled to apply an analog reference voltage to set a differential output of the unified receiver, and further configured to apply a variable digital code to adjust the differential output according to a particular one of the transmitters that is switched to the shared IO channel.Type: ApplicationFiled: March 22, 2024Publication date: July 11, 2024Applicant: NVIDIA Corp.Inventors: Jiwang Lee, Jaewon Lee, Hsuche Nee, Po-Chien Chiang, Wen-Hung Lo, Michael Ivan Halfen, Abhishek Dhir
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Patent number: 11978496Abstract: A method includes generating a differential voltage from a first reference voltage generator; receiving the differential voltage at a second reference voltage generator; dividing the differential voltage at the second reference voltage generator into multiple available reference voltage levels; and selecting one of the available reference voltage levels to apply to a circuit.Type: GrantFiled: April 27, 2022Date of Patent: May 7, 2024Assignee: NVIDIA CORP.Inventors: Jiwang Lee, Jaewon Lee, Po-Chien Chiang, Hsuche Nee, Wen-Hung Lo, Michael Ivan Halfen, Abhishek Dhir
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Patent number: 11973501Abstract: A multi-rank circuit system includes multiple transmitters each switchably coupled to a first end of a shared input/output (IO) channel and a unified receiver coupled to a second end of the shared IO channel. The unified receiver is coupled to apply a preconfigured analog reference voltage to set a differential output of the unified receiver, and further configured to apply a variable digital code to adjust the differential output according to a particular one of the transmitters that is switched to the shared IO channel.Type: GrantFiled: April 27, 2022Date of Patent: April 30, 2024Assignee: NVIDIA CORP.Inventors: Jiwang Lee, Jaewon Lee, Hsuche Nee, Po-Chien Chiang, Wen-Hung Lo, Michael Ivan Halfen, Abhishek Dhir
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Patent number: 11967396Abstract: A multi-rank system includes multiple circuit ranks communicating over a common data line to multiple data receivers, each corresponding to one or more of the ranks and each having a corresponding reference voltage generator and clock timing adjustment circuit, such that a rank to communicate on the shared data line is switched without reconfiguring outputs of either the reference voltage generators or the clock timing adjustment circuits.Type: GrantFiled: April 27, 2022Date of Patent: April 23, 2024Assignee: NVIDIA CORP.Inventors: Wen-Hung Lo, Michael Ivan Halfen, Abhishek Dhir, Jaewon Lee
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Patent number: 11881255Abstract: A multi-rank circuit system utilizing a shared IO channel includes a first stage of multiple selectors coupled to input multiple digital busses, and a second stage including one or more selectors coupled to receive outputs of the first stage of selectors and to individually select one of the outputs of the first stage of selectors to one or more control circuits for IO circuits of the ranks. The system switches one of the ranks to be an active rank on the shared IO channel, and operates the first stage of selectors to select one of the digital busses to the second stage of selectors in advance of switching a next active rank to the shared IO channel.Type: GrantFiled: April 27, 2022Date of Patent: January 23, 2024Assignee: NVIDIA CORP.Inventors: Jiwang Lee, Jaewon Lee, Hsuche Nee, Po-Chien Chiang, Wen-Hung Lo, Abhishek Dhir, Michael Ivan Halfen, Chunjen Su
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Publication number: 20230352081Abstract: A multi-rank circuit system utilizing a shared IO channel includes a first stage of multiple selectors coupled to input multiple digital busses, and a second stage including one or more selectors coupled to receive outputs of the first stage of selectors and to individually select one of the outputs of the first stage of selectors to one or more control circuits for IO circuits of the ranks. The system switches one of the ranks to be an active rank on the shared IO channel, and operates the first stage of selectors to select one of the digital busses to the second stage of selectors in advance of switching a next active rank to the shared IO channel.Type: ApplicationFiled: April 27, 2022Publication date: November 2, 2023Applicant: NVIDIA Corp.Inventors: Jiwang Lee, Jaewon Lee, Hsuche Nee, Po-Chien Chiang, Wen-Hung Lo, Abhishek Dhir, Michael Ivan Halfen, CHUNJEN SU
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Publication number: 20230352077Abstract: A method includes generating a differential voltage from a first reference voltage generator; receiving the differential voltage at a second reference voltage generator; dividing the differential voltage at the second reference voltage generator into multiple available reference voltage levels; and selecting one of the available reference voltage levels to apply to a circuit.Type: ApplicationFiled: April 27, 2022Publication date: November 2, 2023Applicant: NVIDIA Corp.Inventors: Jiwang Lee, Jaewon Lee, Po-Chien Chiang, Hsuche Nee, Wen-Hung Lo, Michael Ivan Halfen, Abhishek Dhir
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Publication number: 20230352067Abstract: A multi-rank system includes multiple circuit ranks communicating over a common data line to multiple data receivers, each corresponding to one or more of the ranks and each having a corresponding reference voltage generator and clock timing adjustment circuit, such that a rank to communicate on the shared data line is switched without reconfiguring outputs of either the reference voltage generators or the clock timing adjustment circuits.Type: ApplicationFiled: April 27, 2022Publication date: November 2, 2023Applicant: NVIDIA Corp.Inventors: Wen-Hung Lo, Michael Ivan Halfen, Abhishek Dhir, Jaewon Lee
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Publication number: 20230353155Abstract: A multi-rank circuit system includes multiple transmitters each switchably coupled to a first end of a shared input/output (IO) channel and a unified receiver coupled to a second end of the shared IO channel. The unified receiver is coupled to apply a preconfigured analog reference voltage to set a differential output of the unified receiver, and further configured to apply a variable digital code to adjust the differential output according to a particular one of the transmitters that is switched to the shared IO channel.Type: ApplicationFiled: April 27, 2022Publication date: November 2, 2023Applicant: NVIDIA Corp.Inventors: Jiwang Lee, Jaewon Lee, Hsuche Nee, Po-Chien Chiang, Wen-Hung Lo, Michael Ivan Halfen, Abhishek Dhir
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Publication number: 20230352078Abstract: The differential voltage output from a first reference voltage generator of a multi-rank circuit is trained on multiple ranks of the multi-rank circuit. Multiple local reference voltage generators are trained to generate reference voltages for communication on the individual ranks, where the reference voltages output by the local reference voltage generators fall within a range of the differential voltage output.Type: ApplicationFiled: April 27, 2022Publication date: November 2, 2023Applicant: NVIDIA Corp.Inventors: Jiwang Lee, Jaewon Lee, Wen-Hung Lo, Michael Ivan Halfen, Abhishek Dhir, Hsuche Nee, Po-Chien Chiang
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Patent number: 11298764Abstract: A circular saw includes a housing, a sawing assembly including a motor and a saw blade located at two opposite sides of the housing and connected together so that the saw blasé can be driven by the motor to saw the workpiece and a saw blade shield secured to the housing and covering a part of the saw blade to prevent the saw blade from cutting the surrounding people, and a prism assembly including a protective cover affixed to the front end of the saw blade shield and a prism located in the protective cover to reflect the image of the saw blade sawing the workpiece through a window of the protective cover to the line of sight of the operator. In this way, the operator can clearly confirm whether the sawing path is skewed with the normal operating posture to improve the efficiency.Type: GrantFiled: June 29, 2020Date of Patent: April 12, 2022Assignee: DURQ MACHINERY CORP.Inventors: Chia-Sheng Liu, Yi-Li Cheng, Wen-Hung Lo
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Publication number: 20210379680Abstract: A circular includes a housing, a sawing assembly including a motor and a saw blade located at two opposite sides of the housing and connected together so that the saw blasé can be driven by the motor to saw the workpiece and a saw blade shield secured to the housing and covering a part of the saw blade to prevent the saw blade from cutting the surrounding people, and a prism assembly including a protective cover affixed to the front end of the saw blade shield and a prism located in the protective cover to reflect the image of the saw blade sawing the workpiece through a window of the protective cover to the line of sight of the operator. In this way, the operator can clearly confirm whether the sawing path is skewed with the normal operating posture to improve the efficiency.Type: ApplicationFiled: June 29, 2020Publication date: December 9, 2021Inventors: Chia-Sheng LIU, Yi-Li CHENG, Wen-Hung LO
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Publication number: 20200355385Abstract: An air conditioning device is provided. The air conditioning device includes a power supplier, a compressor driver, a fan driver, a temperature sensor, a vibration sensor, and an operation processing controller. The power supplier has an input end receiving an input power source and generates a first operating power source and a second operating power source according to the input power source. The compressor driver operates according to the first operating power source to generate a first drive signal to drive a compressor. The fan driver operates according to the first operating power source to generate a second drive signal to drive a fan. The vibration sensor detects vibration information of the air conditioning device.Type: ApplicationFiled: March 16, 2020Publication date: November 12, 2020Applicant: Chizentek Inc.Inventors: Chih-Chuan Liang, Wen-Hung Lo
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Patent number: 10520019Abstract: A slide module comprises an outer rail, a ball rail, first balls and second balls. The outer rail has a first inner surface and a second inner surface. The ball rail has a first holding section and a second holding section. The first balls are rollably disposed in a plurality of first holes of the first holding section in which the first ball is contacted with the first inner surface and the second holding section and distant from the second inner surface. The second balls are rollably disposed in a plurality of second holes of the second holding section in which the second ball is contacted with the second inner surface and the first holding section and distant from the inner surface. Thereby, the ball rail is capable of moving along the axial direction with respect to the outer rail through the first balls and the second balls.Type: GrantFiled: April 11, 2018Date of Patent: December 31, 2019Assignee: SYNCMOLD ENTERPRISE CORP.Inventors: Wen-Hung Lo, Kuang-Yao Wu, Ching-Hui Yen
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Patent number: 10241148Abstract: One embodiment of the present invention sets forth an integrated circuit that includes multiple input/output (I/O) pad groups. Each I/O pad group includes an on-chip star network, multiple I/O pads, multiple test multiplexers, a digital-to-analog converter (DAC), and a wide-range comparator. Each test multiplexer is configured to couple a different I/O pad to the on-chip star network. The DAC is configured to supply at least one of a source current, a sink current, and a first reference voltage to the on-chip star network. The wide-range comparator is configured to compare a voltage present on a first I/O pad included in the plurality of I/O pads with a second reference voltage. Advantageously, IO leakage and DC parametric testing may be performed on integrated circuits with high I/O pad counts using an ATE system with a significantly lower quantity of ATE test channels relative to prior approaches.Type: GrantFiled: August 11, 2015Date of Patent: March 26, 2019Assignee: NVIDIA CORPORATIONInventors: Ashfaq Shaikh, Wen-Hung Lo, Punit Kishore, Amit Sanghani, Krishna Rajan
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Publication number: 20180372153Abstract: A slide module is disclosed, which comprises an outer rail, a ball rail, a plurality of first balls and a plurality of second balls. The outer rail has a first inner surface and a second inner surface. The ball rail has a first holding section and a second holding section. The first balls are rollably disposed in a plurality of first limiting holes of the first holding section in which the first ball is contacted with the first inner surface and the second holding section and distant from the second inner surface. The second balls are rollably disposed in a plurality of second limiting holes of the second holding section in which the second ball is contacted with the second inner surface and the first holding section and distant from the inner surface. Thereby, the ball rail is capable of moving along the axial direction with respect to the outer rail through the first balls and the second balls.Type: ApplicationFiled: April 11, 2018Publication date: December 27, 2018Inventors: Wen-Hung LO, Kuang-Yao WU, Ching-Hui YEN
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Publication number: 20170045575Abstract: One embodiment of the present invention sets forth an integrated circuit that includes multiple input/output (I/O) pad groups. Each I/O pad group includes an on-chip star network, multiple I/O pads, multiple test multiplexers, a digital-to-analog converter (DAC), and a wide-range comparator. Each test multiplexer is configured to couple a different I/O pad to the on-chip star network. The DAC is configured to supply at least one of a source current, a sink current, and a first reference voltage to the on-chip star network. The wide-range comparator is configured to compare a voltage present on a first I/O pad included in the plurality of I/O pads with a second reference voltage. Advantageously, IO leakage and DC parametric testing may be performed on integrated circuits with high I/O pad counts using an ATE system with a significantly lower quantity of ATE test channels relative to prior approaches.Type: ApplicationFiled: August 11, 2015Publication date: February 16, 2017Inventors: Ashfaq SHAIKH, Wen-Hung LO, Punit KISHORE, Amit SANGHANI, Krishna RAJAN
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Patent number: 8891299Abstract: A method for performing a programming operation to a first memory bit and a second memory bit of a device is described. The method includes applying a pulse train voltage to a metal gate of the device and grounding a substrate of the device. By floating/grounding a drain of the device and/or by floating/grounding the source of the device, the first memory and the second memory bit are programmed. The pulse train voltage includes 10 to 1000 pulses. One pulse includes a peak voltage and a base voltage. The peak voltage ranges from 0.5 V to 10 V. A duration of the peak voltage ranges from 1 nanosecond to 1 millisecond. The base voltage is 0 V. A duration of the base voltage ranges from 1 nanosecond to 1 millisecond.Type: GrantFiled: August 9, 2012Date of Patent: November 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Chang Chang, Chih-Hao Dai, Fu-Yen Jian, Wen-Hung Lo, Shih-Chieh Chang, Ying-Lang Wang