Abstract: A data recovery method for a memory device is disclosed. The memory device has a target memory cell, a target word line and an adjacent word line, the adjacent word line is adjacent to the target word line. The target word line is connected to a gate of the target memory cell. The adjacent word line is connected to a gate of an adjacent memory cell, and the adjacent memory cell is adjacent to the target memory cell. The data recovery method includes the following steps. Applying a first program voltage to the target memory cell through the target word line. When applying the first program voltage, concurrently applying a second program voltage to the adjacent memory cell through the adjacent word line.

Abstract: A memory device and a method for operating the same are provided. In an erase operation, a switch voltage is applied to at least one of a string select line or a ground select line of a selected sub-block of a selected block, a gate control voltage is applied to selected word lines of the selected sub-block, and an erase voltage is applied to bit lines and a common source line of the selected sub-block. The switch voltage is smaller than the erase voltage. The gate control voltage is smaller than the switch voltage and the erase voltage.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first substrate, a device layer, a first dielectric layer, a second dielectric layer, a second substrate, and a circuit layer. The device layer is disposed on the first substrate. The first dielectric layer is disposed on the device layer. The second dielectric layer is disposed on the first dielectric layer. The second substrate is disposed on the second dielectric layer. The circuit layer is disposed on the second substrate.

Abstract: An operation method for a memory device is provided. The operation method includes: increasing a dummy word line voltage to a first dummy word line voltage during a pre-turn on period; increasing the dummy word line voltage from the first dummy word line voltage to a second dummy word line voltage during a read period; and lowering the dummy word line voltage after the read period is finished. Wherein the first dummy word line voltage is lower than the second dummy word line voltage.

Abstract: A memory device and a method for fabricating the memory device are provided. The memory device includes a substrate having an upper surface; a stacked structure disposed on the upper surface of the substrate, wherein the stacked structure includes a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer and a third insulating layer sequentially stacked on the substrate; a plurality of channel structures penetrating the stacked structure and electrically connected to the substrate, wherein each of the channel structures includes an upper portion corresponding to the second conductive layer and a lower portion corresponding to the first conductive layer; a memory layer disposed between the second conductive layer and the upper portion; and a plurality of isolation structures penetrating the stacked structure to separate the stacked structure into a plurality of sub-stacks.

Abstract: An operation method for a memory device is provided. The operation method includes: increasing a dummy word line voltage to a first dummy word line voltage during a pre-tum on period; increasing the dummy word line voltage from the first dummy word line voltage to a second dummy word line voltage during a read period; and lowering the dummy word line voltage after the read period is finished. Wherein the first dummy word line voltage is lower than the second dummy word line voltage.

Abstract: An operation method for a memory device is provided. The operation method includes: increasing a dummy word line voltage to a first dummy word line voltage during a pre-tum on period; increasing the dummy word line voltage from the first dummy word line voltage to a second dummy word line voltage during a read period; and lowering the dummy word line voltage after the read period is finished. Wherein the first dummy word line voltage is lower than the second dummy word line voltage.

Abstract: An operation method for a memory device is provided. The operation method includes: increasing an adjacent word line voltage to a first adjacent word line voltage during a pre-turn on period; and increasing the adjacent word line voltage from the first adjacent word line voltage to a second adjacent word line voltage after the pre-turn on period is finished; wherein the first adjacent word line voltage is lower than the second adjacent word line voltage; the adjacent word line voltage is applied to at least one adjacent word line, and the at least one adjacent word line is adjacent to a selected word line.

Abstract: Provided are a memory device and an operation method thereof. The memory device includes a plurality of word lines. The operation method comprising: performing a pre-fill operation on the word lines, in a first loop, applying a selected word line voltage on a first selected word line group and applying an unselected word line voltage on a first unselected word line group, and in a second loop, applying the selected word line voltage on a second selected word line group and applying the unselected word line voltage on a second unselected word line group, the first selected word line group being different from the second selected word line group, and the first unselected word line group being different from the second unselected word line group; performing an erase operation on the word lines; and performing a programming operation on the word lines.

Abstract: A memory device and a method for fabricating the memory device are provided. The memory device includes a substrate having an upper surface; a stacked structure disposed on the upper surface of the substrate, wherein the stacked structure includes a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer and a third insulating layer sequentially stacked on the substrate; a plurality of channel structures penetrating the stacked structure and electrically connected to the substrate, wherein each of the channel structures includes an upper portion corresponding to the second conductive layer and a lower portion corresponding to the first conductive layer; a memory layer disposed between the second conductive layer and the upper portion; and a plurality of isolation structures penetrating the stacked structure to separate the stacked structure into a plurality of sub-stacks.

Abstract: A memory device includes a substrate having an upper surface; a stacked structure disposed on the upper surface of the substrate, wherein the stacked structure includes a first insulating layer, a first conductive layer, a second insulating layer; a second conductive layer and a third insulating layer sequentially stacked on the substrate; a plurality of channel structures penetrating the stacked structure and electrically connected to the substrate, wherein each of the channel structures includes an upper portion corresponding to the second conductive layer and a lower portion corresponding to the first conductive layer; a memory layer disposed between the second conductive layer and the upper portion; and a plurality of isolation structures penetrating the stacked structure to separate the stacked structure into a plurality of sub-stacks.

Abstract: A 3D memory device includes a substrate, stacked structures formed on the substrate, common source line (CSL) contacts, and NOR flash memories. The substrate has CSLs and memory cell regions alternately arranged along one direction in parallel. The stacked structures are located on the memory cell regions and include a ground select line (GSL) layer and a word line (WL) layer. The CSL contacts are disposed along another direction to connect the CSLs. The NOR flash memories are disposed in the memory cell regions, and each of the NOR flash memories includes at least an epitaxial pillar through the stacked structure, a charge-trapping layer located between the epitaxial pillar and the WL layer, and a high-k layer located between the charge-trapping layer and the WL layer. The epitaxial pillar has a retracted sidewall at a position passing through the GSL layer.

Abstract: A 3D memory device includes a substrate, stacked structures formed on the substrate, common source line (CSL) contacts, and NOR flash memories. The substrate has CSLs and memory cell regions alternately arranged along one direction in parallel. The stacked structures are located on the memory cell regions and include a ground select line (GSL) layer and a word line (WL) layer. The CSL contacts are disposed along another direction to connect the CSLs. The NOR flash memories are disposed in the memory cell regions, and each of the NOR flash memories includes at least an epitaxial pillar through the stacked structure, a charge-trapping layer located between the epitaxial pillar and the WL layer, and a high-k layer located between the charge-trapping layer and the WL layer. The epitaxial pillar has a retracted sidewall at a position passing through the GSL layer.

Abstract: A memory device and a programming method thereof are provided. The memory device includes a memory array, a plurality of word lines and a voltage generator. During a programming procedure, one of the word lines is at a selected state and others of the word lines are at a deselected state. Some of the word lines, which are at the deselected state, are classified into a first group and a second group. The first group and the second group are respectively located at two sides of the word line, which is at the selected state. The voltage generator provides a programming voltage to the word line, which is at the select state, during a programming duration. The voltage generator provides a first two-stage voltage waveform to the word lines in the first group and provides a second two-stage voltage waveform to the word lines in the second group.

Abstract: A memory device includes a substrate having an upper surface; a stacked structure disposed on the upper surface of the substrate, wherein the stacked structure includes a first insulating layer; a first conductive layer, a second insulating layer; a second conductive layer and a third insulating layer sequentially stacked on the substrate; a plurality of channel structures penetrating the stacked structure and electrically connected to the substrate; wherein each of the channel structures includes an upper portion corresponding to the second conductive layer and a lower portion corresponding to the first conductive layer; a memory layer disposed between the second conductive layer and the upper portion; and a plurality of isolation structures penetrating the stacked structure to separate the stacked structure into a plurality of sub-stacks.

Abstract: Provided is an erase method for a multi-tier three-dimension (3D) memory including a plurality of tiers and a plurality of blocks, each of the tiers including a plurality of word lines. The erase method includes: in erasing a selected block among the plurality of blocks, in a current iteration, selecting at least one tier among the plurality of tiers to be erased by a first erase voltage; determining whether the at least one tier passes erase verification; and if the at least one tier passes erase verification, in a next iteration, inhibiting the at least tier which already passes erase verification from erase.

Abstract: A memory device includes a conductive strip stack structure having conductive strips and insulating layers stacked in a staggered manner and a channel opening passing through the conductive strips and the insulating layer; a memory layer disposed in the channel opening and overlying the conductive strips; a channel layer overlying the memory layer; a semiconductor pad extending upwards from a bottom of the channel opening beyond an upper surface of a bottom conductive strip, in contact with the channel layer, and electrically isolated from the conductive strips; wherein the channel layer includes a first portion having a first doping concentration and a second portion having a second doping concentration disposed on the first portion.

Abstract: A memory device includes a substrate, a stacked structure, a plurality of channel structures, a plurality of memory layers, and a plurality of shallow isolation structures. The substrate has an upper surface. The stacked structure is disposed on an upper surface of the substrate, wherein the stacked structure includes a plurality of insulating layers and a plurality of conductive layers alternatively stacked on the upper surface. The channel structures penetrate portions of the stacked structure and are electrically connected to the substrate. The memory layers surround the corresponding ones of the channel structures. The shallow isolation structures extend from a top surface of the stacked structure toward the substrate, wherein each of the shallow isolation structures includes a substance having a dielectric constant of less than 3.9.

Abstract: A memory device is provided. The memory device includes a plurality of memory cell blocks and a source voltage generator. Each of the memory cell blocks has at least one memory cell. The source voltage generator is coupled to the plurality of memory cell blocks and configured to cause a source voltage of the memory cell block to be a first voltage according to that a memory cell in each of the memory cell blocks is in a selected state and cause a source voltage of the memory cell block to be a second voltage according to that all memory cells in each of the memory cell blocks are in an unselected state, wherein an absolute value of the first voltage is less than an absolute value of the second voltage. In addition, an operating method of the memory device is also provided.

Abstract: A memory device includes a conductive strip stack structure having conductive strips and insulating layers stacked in a staggered manner and a channel opening passing through the conductive strips and the insulating layer; a memory layer disposed in the channel opening and overlying the conductive strips; a channel layer overlying the memory layer; a semiconductor pad extending upwards from a bottom of the channel opening beyond an upper surface of a bottom conductive strip, in contact with the channel layer, and electrically isolated from the conductive strips; wherein the channel layer includes a first portion having a first doping concentration and a second portion having a second doping concentration disposed on the first portion.