Abstract: A memory device is provided. The memory device includes a plurality of memory cell blocks and a source voltage generator. Each of the memory cell blocks has at least one memory cell. The source voltage generator is coupled to the plurality of memory cell blocks and configured to cause a source voltage of the memory cell block to be a first voltage according to that a memory cell in each of the memory cell blocks is in a selected state and cause a source voltage of the memory cell block to be a second voltage according to that all memory cells in each of the memory cell blocks are in an unselected state, wherein an absolute value of the first voltage is less than an absolute value of the second voltage. In addition, an operating method of the memory device is also provided.

Abstract: A programming operation for high density memory, like 3D NAND flash memory, modifies the waveforms applied during program operations to mitigate unwanted disturbance of memory cells not selected for programming during the operation. Generally, the method provides for applying a bias arrangement during an interval of time between program verify pass voltages and program pass voltages in a program sequence that can include a soft ramp down, and pre-turn-on voltages designed to reduce variations in the potential distribution on floating channels of unselected NAND strings during a program operation.

Abstract: A programming operation for high density memory, like 3D NAND flash memory, modifies the waveforms applied during program operations to mitigate unwanted disturbance of memory cells not selected for programming during the operation. Generally, the method provides for applying a bias arrangement during an interval of time between program verify pass voltages and program pass voltages in a program sequence that can include a soft ramp down, and pre-turn-on voltages designed to reduce variations in the potential distribution on floating channels of unselected NAND strings during a program operation.

Abstract: A method for programming a non-volatile memory and a memory system are provided. Each of multiple cells of the non-volatile memory stores data having at least 2 bits. The method includes the following steps. At least one programming pulse is provided for programming a target cell of the cells. At least one program-verify pulse is provided for verifying whether the target cell is successfully programmed. It is determined that whether a threshold voltage of the target cell is greater than or equal to a program-verify voltage. When the threshold voltage is greater than or equal to the program-verify voltage, the target cell is set as successfully programmed. Next, a post-verifying operation is performed to the successfully programmed cell. The post-verifying operation includes determining whether the threshold voltage of the target cell is greater than or equal to a post-verifying voltage.

Abstract: The method for programming a non-volatile memory includes the following steps. Perform a program and program verify operation for a memory cell in the non-volatile memory, wherein the program and program verify operation includes applying a sequence of incremental step pulses to the memory cell. Perform a post-verifying operation for the memory cell after the memory cell passes the program and program verify operation. Apply a post-programming pulse to the memory cell if the memory cell fails the post-verifying operation, wherein the amplitude of the post-programming pulse is greater than the amplitude of the last pulse in the sequence of incremental step pulses. Perform a read operation to the non-volatile memory to obtain a failed bit count corresponding to the read operation. Adjust a read reference voltage of the read operation to minimize the failed bit count.

Abstract: An erase-verify method for a three-dimensional (3D) memory and a memory system are provided. The 3D memory includes at least one memory cell string including a plurality of memory cells, and the memory cells include a first group of memory cells and a second group of memory cells. Each of the memory cells is coupled to a word line. The method comprises the following steps. A first erase-verify operation is performed on the first group of memory cells. After performing the first erase-verify operation on the first group of memory cells, a second erase-verify operation is performed on the second group of memory cells in condition that the first group of memory cells are verified as erased successfully.

Abstract: An erase-verify method for a three-dimensional (3D) memory and a memory system are provided. The 3D memory includes at least one memory cell string including a plurality of memory cells, and the memory cells include a first group of memory cells and a second group of memory cells. Each of the memory cells is coupled to a word line. The method comprises the following steps. A first erase-verify operation is performed on the first group of memory cells. After performing the first erase-verify operation on the first group of memory cells, a second erase-verify operation is performed on the second group of memory cells in condition that the first group of memory cells are verified as erased successfully.

Abstract: A method for programming a non-volatile memory and a memory system are provided. Each of multiple cells of the non-volatile memory stores data having at least 2 bits. The method includes the following steps. At least one programming pulse is provided for programming a target cell of the cells. At least one program-verify pulse is provided for verifying whether the target cell is successfully programmed. It is determined that whether a threshold voltage of the target cell is greater than or equal to a program-verify voltage. When the threshold voltage is greater than or equal to the program-verify voltage, the target cell is set as successfully programmed. Next, a post-verifying operation is performed to the successfully programmed cell. The post-verifying operation includes determining whether the threshold voltage of the target cell is greater than or equal to a post-verifying voltage.

Abstract: An operation method of a memory cell includes steps of applying a pre pulse before a read pulse is applied, wherein the pre pulse is larger than a maximum threshold voltage or less than a lowest threshold voltage.

Abstract: A memory structure includes a memory cell, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. The first charge storage structure is a singular charge storage unit and the second charge storage structure comprises two charge storage units which are physically separated. A channel output line physically connected to the channel layer. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source or drain and a second source or drain are disposed on the first dielectric layer and located at two sides of the channel layer.

Abstract: A memory structure includes a memory cell, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. The first charge storage structure is a singular charge storage unit and the second charge storage structure comprises two charge storage units which are physically separated. A channel output line physically connected to the channel layer. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source or drain and a second source or drain are disposed on the first dielectric layer and located at two sides of the channel layer.

Abstract: A memory device is provided. The memory device includes a substrate, a plurality of semiconductor strip structures, a first doped region, a plurality of second doped regions, a plurality of first contacts, and a plurality of second contacts. Each of the semiconductor strip structures extends along a first direction. The first doped region includes a plurality of first portions and a second portion. Each of the first portions is located on a lower part of the corresponding semiconductor strip structure. The second portion is located on a surface of the substrate, and the first portions are connected to the second portion. Each of the second doped regions is located on an upper part of the corresponding semiconductor strip structure. Each of the first contacts is electrically connected to the second portion of the first doped region. Each of the second contacts is electrically connected to the corresponding second doped region.

Abstract: A memory device includes a substrate, a first doped region, composite structures, word lines, and a charge storage layer. The first doped region is disposed on a surface of the substrate. The composite structures are disposed on the first doped region. Each composite structure includes two semiconductor fin structures and a dielectric layer. Each semiconductor fin structure includes a second doped region disposed at an upper portion of the semiconductor fin structure and a body region disposed between the second doped region and the first doped region. The dielectric layer is disposed between the semiconductor fin structures. The word lines are disposed on the substrate. Each word line covers a partial sidewall and a partial top of each composite structure. The charge storage layer is disposed between the composite structures and the word lines.

Abstract: A memory device is provided. The memory device includes a plurality of stack structures, a plurality of first stepped contacts, and a plurality of second stepped contacts. Each of the stack structures extends in a first direction, and includes a first semiconductor layer and a second semiconductor layer. The second semiconductor layer is disposed above the first semiconductor layer. Each of the first stepped contacts extends in a second direction, and a bottom surface thereof is electrically connected to the first semiconductor layers of an i+1th stack structure and an i+2th stack structure, wherein i is an odd number. Each of the second stepped contacts extends in the second direction, and a bottom surface thereof is electrically connected to the second semiconductor layers of an nth stack structure and the i+1th stack structure. The first direction is different from the second direction.

Abstract: A memory structure includes a memory cell, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. The first charge storage structure is a singular charge storage unit and the second charge storage structure comprises two charge storage units which are physically separated. A channel output line physically connected to the channel layer. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source or drain and a second source or drain are disposed on the first dielectric layer and located at two sides of the channel layer.

Abstract: A nonvolatile memory cell has a semiconductor substrate, a multilayer stack including a charge trapping layer over a floating gate, a top conductive layer, and circuitry controlling program and erase operations on the nonvolatile memory cell. The program and erase operations change a first charge density on the floating gate by a larger magnitude than a second charge density on the charge trapping dielectric layer.

Abstract: Provided is a method for fabricating a memory device, including the following steps. A plurality of semiconductor fin structures is formed on a substrate. Each semiconductor fin structure includes a first doped region and a body region on which the first doped region is disposed, and a trench is disposed between adjacent two semiconductor fin structures. A second doped region is formed in the substrate under the body regions of the semiconductor fin structures and the trenches. A plurality of first contacts are formed on the substrate. A plurality of second contacts are formed on the substrate. Each second contact is electrically connected with the corresponding first doped region.

Abstract: A programming method for a memory device is provided. The memory device includes a first transistor, a memory cell string, and a second transistor which are electrically connected in series. The memory cell string includes a target memory cell, first and second peripheral memory cells adjacent to the target memory cell, and a plurality of non-target memory cells which are not adjacent to the target memory cell. The programming method includes following steps. The first transistor is turned on, and the second transistor is turned off. A pass voltage is applied to turn on the non-target memory cells, and an assistant voltage is applied to turn on the first and second peripheral memory cells. A programming voltage is applied to program the target memory cell. The assistant voltage is greater than the pass voltage and is less than the programming voltage.

Abstract: A read only memory including a substrate, a source region and a drain region, a charge storage structure, a gate, and a local extreme doping region is provided. The source region and the drain region are disposed in the substrate, the charge storage structure is located on the substrate between the source region and the drain region, and the gate is configured on the charge storage structure. The local extreme doping region is located in the substrate between the source region and the drain region and includes a low doping concentration region and at least one high doping concentration region. The high doping concentration region is disposed between the low doping concentration region and one of the source region and the drain region, and a doping concentration of the high doping concentration region is three times or more than three times a doping concentration of the low doping concentration region.

Abstract: Provided is a memory cell including a substrate, two doped regions of a first conductivity type, one doped region of a second conductivity type, two stacked structures, and a first isolation structure. The doped regions of the first conductivity type are respectively disposed in the substrate. The doped region of the second conductivity type is disposed in the substrate between the two doped regions of the first conductivity type. The stacked structures are disposed on the substrate and respectively cover the corresponding doped regions of the first conductivity type and a portion of the doped region of the second conductivity type. Each of the stacked structures includes one charge storage layer. The first isolation structure completely covers and is in contact with the bottom surface of each of the doped regions of the first conductivity type and the bottom surface of the doped region of the second conductivity type.