Abstract: An operation of a VM running first and second VM components is suspended so that a servicing operation for the VM can be performed. The VM has devices directly attached to it. A state of the first VM components is saved. An identification pointer for the second VM components is saved in a portion of the computing system physical memory without removing any underlying data structures of second VM components from computing system physical hardware. The directly attached devices remain configured as attached to the VM and remain configured to communicate with the VM while the VM is suspended and while the servicing operation is performed. The first VM components are shut down and then restored at the completion of the servicing operation using the saved state. The restored first VM components are reconnected to the second VM components using the identification pointers. The operation of the VM is restored.

Abstract: Communicating a low-latency event across a virtual machine boundary. Based on an event signaling request by a first process running at a first virtual machine, the first virtual machine updates a shared register that is accessible by a second virtual machine. Updating the shared register includes updating a signal stored in the shared register. The first virtual machine sends an event signal message, which includes a register identifier, through a virtualization fabric to the second virtual machine. The second virtual machine receives the event signaling message and identifies the register identifier from the message. Based on the register identifier, the second virtual machine reads the shared register, identifying a value of the signal stored in the shared register. Based at least on the value of the signal comprising a first value, the second virtual machine signals a second process running at the second virtual machine.

Abstract: A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion.

Abstract: Communicating a low-latency event across a virtual machine boundary. Based on an event signaling request by a first process running at a first virtual machine, the first virtual machine updates a shared register that is accessible by a second virtual machine. Updating the shared register includes updating a signal stored in the shared register. The first virtual machine sends an event signal message, which includes a register identifier, through a virtualization fabric to the second virtual machine. The second virtual machine receives the event signaling message and identifies the register identifier from the message. Based on the register identifier, the second virtual machine reads the shared register, identifying a value of the signal stored in the shared register. Based at least on the value of the signal comprising a first value, the second virtual machine signals a second process running at the second virtual machine.

Abstract: A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion.

Abstract: An operation of a VM running first and second VM components is suspended so that a servicing operation for the VM can be performed. The VM has devices directly attached to it. A state of the first VM components is saved. An identification pointer for the second VM components is saved in a portion of the computing system physical memory without removing any underlying data structures of second VM components from computing system physical hardware. The directly attached devices remain configured as attached to the VM and remain configured to communicate with the VM while the VM is suspended and while the servicing operation is performed. The first VM components are shut down and then restored at the completion of the servicing operation using the saved state. The restored first VM components are reconnected to the second VM components using the identification pointers. The operation of the VM is restored.

Abstract: The semiconductor device includes a substrate, an epi-layer, a first etch stop layer, an interlayer dielectric (ILD) layer, a second etch stop layer, a protective layer, a liner, a silicide cap and a contact plug. The substrate has a first portion and a second portion. The epi-layer is disposed in the first portion. The first etch stop layer is disposed on the second portion. The ILD layer is disposed on the first etch stop layer. The second etch stop layer is disposed on the ILD layer, in which the first etch stop layer, the ILD layer and the second etch stop layer form a sidewall surrounding the first portion. The protective layer is disposed on the sidewall. The liner is disposed on the protective layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the liner.

Abstract: The semiconductor device includes a substrate, an epi-layer, a first etch stop layer, an interlayer dielectric (ILD) layer, a second etch stop layer, a protective layer, a liner, a silicide cap and a contact plug. The substrate has a first portion and a second portion. The epi-layer is disposed in the first portion. The first etch stop layer is disposed on the second portion. The ILD layer is disposed on the first etch stop layer. The second etch stop layer is disposed on the ILD layer, in which the first etch stop layer, the ILD layer and the second etch stop layer form a sidewall surrounding the first portion. The protective layer is disposed on the sidewall. The liner is disposed on the protective layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the liner.

Abstract: A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion.

Abstract: A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion.

Abstract: A mapping table updating method, a memory control circuit unit and a memory storage device are provided. The mapping table updating method includes: recording first mapping information as a mapping relation between a first virtual block and a first physical erasing unit; recording second mapping information as a mapping relation between the first virtual block and a second virtual block, and the second virtual block is mapped to the first physical erasing unit; and updating the second mapping information as a mapping relation between the first virtual block and a third virtual block if copying data belonging to the first physical erasing unit to a second physical erasing unit, and the third virtual block is mapped to the second physical erasing unit.

Abstract: Provided is a FinFET device including a substrate having at least one fin of the FinFET device, a gate stack, a spacer, a strained layer, a composite etching stop layer, a dielectric layer and a connector. The gate stack is across the at least one fin of the FinFET device. The spacer is on a sidewall of the gate stack. The strained layer is in the substrate aside the gate stack. The composite etching stop layer is on the spacer and on the strained layer. Besides, the composite etching stop layer is thicker on the spacer but thinner on the strained layer. The dielectric layer is on the composite etching stop layer. The connector is over and electrically connected to the strained layer. A first upper portion of a first sidewall of the connector is in contact with the composite etching stop layer, and a second upper portion of a second sidewall of the connector is separate from the composite etching stop layer by the dielectric layer therebetween.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate stack structure formed over a substrate. The gate stack structure includes a gate electrode structure having a first portion and a second portion and a first conductive layer below the gate electrode structure. In addition, the first portion of the gate electrode structure is located over the second portion of the gate electrode structure, and a width of a top surface of the first portion of the gate electrode structure is greater than a width of a bottom surface of the second portion of the gate electrode structure.

Abstract: A semiconductor device includes: a gate structure on a substrate; a raised source/drain region adjacent to the gate structure; a channel region under the gate structure; and a protection layer between the substrate and the raised source/drain region. The protection layer is interposed between the substrate and the raised source/drain region. An atom stacking arrangement of the protection layer is different from the substrate and the raised source/drain region.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate stack structure formed over a substrate. The gate stack structure includes a gate electrode structure having a first portion and a second portion and a first conductive layer below the gate electrode structure. In addition, the first portion of the gate electrode structure is located over the second portion of the gate electrode structure, and a width of a top surface of the first portion of the gate electrode structure is greater than a width of a bottom surface of the second portion of the gate electrode structure.

Abstract: A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion.

Abstract: A gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region over the semiconductor substrate, a first work function metal layer disposed over the gate dielectric layer and lining a bottom surface of an inner sidewall of the spacer, and a filling metal partially wrapped by the first work function metal layer. The filling metal includes a first portion and a second portion, wherein the first portion is between the second portion and the semiconductor substrate, and the second portion is wider than the first portion.

Abstract: The semiconductor device includes a substrate, an epi-layer, a first etch stop layer, an interlayer dielectric (ILD) layer, a second etch stop layer, a protective layer, a liner, a silicide cap and a contact plug. The substrate has a first portion and a second portion. The epi-layer is disposed in the first portion. The first etch stop layer is disposed on the second portion. The ILD layer is disposed on the first etch stop layer. The second etch stop layer is disposed on the ILD layer, in which the first etch stop layer, the ILD layer and the second etch stop layer form a sidewall surrounding the first portion. The protective layer is disposed on the sidewall. The liner is disposed on the protective layer. The silicide cap is disposed on the epi-layer. The contact plug is disposed on the silicide cap and surrounded by the liner.

Abstract: Provided is a FinFET device including a substrate having at least one fin of the FinFET device, a gate stack, a spacer, a strained layer, a composite etching stop layer, a dielectric layer and a connector. The gate stack is across the at least one fin of the FinFET device. The spacer is on a sidewall of the gate stack. The strained layer is in the substrate aside the gate stack. The composite etching stop layer is on the spacer and on the strained layer. Besides, the composite etching stop layer is thicker on the spacer but thinner on the strained layer. The dielectric layer is on the composite etching stop layer. The connector is over and electrically connected to the strained layer. A first upper portion of a first sidewall of the connector is in contact with the composite etching stop layer, and a second upper portion of a second sidewall of the connector is separate from the composite etching stop layer by the dielectric layer therebetween.

Abstract: An apparatus for cleaning a glass sheet moving along a conveyed direction is disclosed herein. The apparatus comprises a first plurality of spraying devices coupled to a water supply and positioned away from a first surface of the glass sheet in a first angle measured from the first surface of the glass sheet, and a control unit configured to supply water from the water supply into the first plurality of spraying devices such that the first plurality of spraying devices spray water from the water supply in a first plurality of spraying sections at the first angle over an edge of the glass sheet, thereby forming a first cleaning zone on the first surface of the glass sheet.