Patents by Inventor Wen-Jiun Liu
Wen-Jiun Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230215807Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.Type: ApplicationFiled: January 9, 2023Publication date: July 6, 2023Inventors: Wen-Jiun LIU, Chen-Yuan KAO, Hung-Wen SU, Ming-Hsing TSAI, Syun-Ming JANG
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Patent number: 11552018Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.Type: GrantFiled: May 3, 2021Date of Patent: January 10, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Jiun Liu, Chen-Yuan Kao, Hung-Wen Su, Ming-Hsing Tsai, Syun-Ming Jang
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Publication number: 20210272910Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.Type: ApplicationFiled: May 3, 2021Publication date: September 2, 2021Inventors: Wen-Jiun LIU, Chen-Yuan Kao, Hung-Wen Su, Ming-Hsing Tsai, Syun-Ming Jang
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Patent number: 10998269Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.Type: GrantFiled: June 22, 2020Date of Patent: May 4, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Jiun Liu, Chen-Yuan Kao, Hung-Wen Su, Ming-Hsing Tsai, Syun-Ming Jang
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Publication number: 20200388575Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.Type: ApplicationFiled: June 22, 2020Publication date: December 10, 2020Inventors: Wen-Jiun Liu, Chen-Yuan Kao, Hung-Wen Su, Ming-Hsing Tsai, Syun-Ming Jang
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Patent number: 10692814Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.Type: GrantFiled: January 9, 2017Date of Patent: June 23, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Jiun Liu, Chen-Yuan Kao, Hung-Wen Su, Ming-Hsing Tsai, Syun-Ming Jang
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Patent number: 9953868Abstract: A method of forming a conductive structure includes forming a first opening and a second opening in a dielectric layer on a substrate, wherein the first opening is narrower than the second opening. The method further includes depositing a diffusion barrier layer to line the first opening and the second opening. The method further includes forming a metal layer over the diffusion barrier layer to fill at least portions of the first opening and the second opening, wherein a maximum thickness of the metal layer in the first opening is greater than a maximum thickness of the metal layer in the second opening.Type: GrantFiled: January 5, 2016Date of Patent: April 24, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-An Chen, Wen-Jiun Liu, Chun-Chieh Lin, Hung-Wen Su, Ming Hsing Tsai, Syun-Ming Jang
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Publication number: 20170160528Abstract: A light collecting module that includes at least one light concentrating unit, at least one collimating unit, and a focusing mirror is provided. The light concentrating unit has a light input end and a light output end opposite to the light input end, and the light concentrating unit is configured to collect lights at various incident angles through the light input end and concentrate the lights on the light output end. The collimating unit collimates the lights from the light output end of the light concentrating unit. The focusing mirror focuses the collimated lights from the collimating unit on a focus of the focusing mirror.Type: ApplicationFiled: December 4, 2015Publication date: June 8, 2017Inventors: Zong-Hsin Liu, Fu-Chuan Hsu, Cheng-Tang Pan, Yen-Po Sun, Chung-Kun Yen, Wen-Jiun Liu, Hsuan-Cheng Liu
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Publication number: 20170133324Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.Type: ApplicationFiled: January 9, 2017Publication date: May 11, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Jiun LIU, Chen-Yuan KAO, Hung-Wen SU, Ming-Hsing TSAI, Syun-Ming JANG
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Patent number: 9564398Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.Type: GrantFiled: March 15, 2013Date of Patent: February 7, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Jiun Liu, Chen-Yuan Kao, Hung-Wen Su, Mingh-Hsing Tsai, Syun-Ming Jang
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Publication number: 20160133514Abstract: A method of forming a conductive structure includes forming a first opening and a second opening in a dielectric layer on a substrate, wherein the first opening is narrower than the second opening. The method further includes depositing a diffusion barrier layer to line the first opening and the second opening. The method further includes forming a metal layer over the diffusion barrier layer to fill at least portions of the first opening and the second opening, wherein a maximum thickness of the metal layer in the first opening is greater than a maximum thickness of the metal layer in the second opening.Type: ApplicationFiled: January 5, 2016Publication date: May 12, 2016Inventors: Chien-An Chen, Wen-Jiun Liu, Chun-Chieh Lin, Hung-Wen Su, Ming-Hsing Tsai, Syun-Ming Jang
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Publication number: 20160105096Abstract: A power factor correction (PFC) controller and a power supply apparatus using the same are provided. The PFC controller includes a driving signal generation circuit and a zero-current prediction circuit. The driving signal generation circuit generates a driving signal to drive a power switch according to a control signal, where the power switch is switched in response to the driving signal, so as to convert an input voltage into an output voltage. The zero-current prediction circuit is coupled to the driving signal generation circuit and performs a capacitance charge/discharge operation, and thus obtains a charge/discharge time characteristic related to a zero-current timing. The zero-current prediction circuit generates the control signal to control operation of the driving signal generation circuit according to the charge/discharge time characteristic.Type: ApplicationFiled: October 13, 2014Publication date: April 14, 2016Inventors: Ke-Horng Chen, Hsin-Yu Luo, Wen-Jiun Liu, Che-Hao Meng, Chih-Wei Chang
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Patent number: 9269612Abstract: An interconnect structure includes a first trench and a second trench. The second trench is wider than the first trench. Both trenches are lined with a diffusion barrier layer, and a first conductive layer is deposited over the diffusion barrier layer. A metal cap layer is deposited over the first conductive layer. A second conductive layer is deposited over the metal cap layer in the second trench.Type: GrantFiled: March 29, 2012Date of Patent: February 23, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-An Chen, Wen-Jiun Liu, Chun-Chieh Lin, Hung-Wen Su, Ming-Hsing Tsai, Syun-Ming Jang
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Patent number: 9214383Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate. A patterned adhesion layer is formed on the substrate. A metal layer is deposited on the patterned adhesion layer. An elevated temperature thermal process is applied to agglomerate the metal layer to form a self-forming-metal-feature (SFMF) and a dielectric layer is deposited between SFMFs.Type: GrantFiled: January 18, 2013Date of Patent: December 15, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Jiun Liu, Chien-An Chen, Ya-Lien Lee, Hung-Wen Su, Minghsing Tsai, Syun-Ming Jang
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Patent number: 9118190Abstract: A charging balancing system and method thereof based on a battery operating process and are disclosed. This is done by detecting a state of all cells in a detecting battery assembly to generate detection parameters, analyzing the detection parameters to produce an operating process, selecting at least one of residual power estimation methods according to the operating process, so as to calculate a residual power of each cell, and adjusting the charging current and charging time for each cell according to the residual power. As such, the efficiency of charging balancing is promoted.Type: GrantFiled: October 30, 2013Date of Patent: August 25, 2015Assignee: Metal Industries Research & Development CentreInventors: Sheng-Wei Chen, Kuan-Yuen Liao, Wen-Jiun Liu, Jeng-Chyan Lin
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Publication number: 20150115892Abstract: A charging balancing system and method thereof based on a battery operating process and are disclosed. This is done by detecting a state of all cells in a detecting battery assembly to generate detection parameters, analyzing the detection parameters to produce an operating process, selecting at least one of residual power estimation methods according to the operating process, so as to calculate a residual power of each cell, and adjusting the charging current and charging time for each cell according to the residual power. As such, the efficiency of charging balancing is promoted.Type: ApplicationFiled: October 30, 2013Publication date: April 30, 2015Applicant: METAL INDUSTRIES RESEARCH & DEVELOPMENT CENTREInventors: Sheng-Wei CHEN, Kuan-Yuen LIAO, Wen-Jiun LIU, Jeng-Chyan LIN
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Patent number: 8980745Abstract: A semiconductor device, an interconnect structure, and methods of forming the same are disclosed. An embodiment is a method of forming a semiconductor device, the method including forming a first dielectric layer over a substrate, forming a first conductive layer in the first dielectric layer, and removing a first portion of the first conductive layer to form at least two conductive lines in the first dielectric layer, the at least two conductive lines being separated by a first spacing. The method further includes forming a capping layer on the at least two conductive lines, and forming an etch stop layer on the capping layer and the first dielectric layer.Type: GrantFiled: September 5, 2013Date of Patent: March 17, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Szu-Ping Tung, Huang-Yi Huang, Wen-Jiun Liu, Ching-Hua Hsieh, Minghsing Tsai
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Publication number: 20150061141Abstract: A semiconductor device, an interconnect structure, and methods of forming the same are disclosed. An embodiment is a method of forming a semiconductor device, the method including forming a first dielectric layer over a substrate, forming a first conductive layer in the first dielectric layer, and removing a first portion of the first conductive layer to form at least two conductive lines in the first dielectric layer, the at least two conductive lines being separated by a first spacing. The method further includes forming a capping layer on the at least two conductive lines, and forming an etch stop layer on the capping layer and the first dielectric layer.Type: ApplicationFiled: September 5, 2013Publication date: March 5, 2015Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Szu-Ping Tung, Huang-Yi Huang, Wen-Jiun Liu, Ching-Hua Hsieh, Minghsing Tsai
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Publication number: 20140264866Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: Wen-Jiun Liu, Chen-Yuan Kao, Hung-Wen Su, Mingh-Hsing Tsai, Syun-Ming Jang
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Publication number: 20140095090Abstract: A residual battery capacity estimation system that adds two mutually perpendicular components and the method thereof are provided. The mechanism detects the battery voltage, current and temperature as the sensing parameters, and uses the preset electrical characteristic parameters and capacity change to look up a table for the battery dynamic internal resistance component. The mechanism uses the sensing parameters and the Coulomb counting method to calculate the component of the battery Coulomb counting charge. Afterwards, the battery dynamic internal resistance component and the battery Coulomb counting capacity component are then added to calculate the actual residual power of the battery. The mechanism achieves the goal of increasing the accuracy in estimating the battery residual power.Type: ApplicationFiled: December 26, 2012Publication date: April 3, 2014Applicant: METAL INDUSTRIES RESEARCH & DEVELOPMENT CENTREInventors: Sheng Wei CHEN, Kuan Yuen LIAO, Wen Jiun LIU, Kai Chung LIU, Li Hsuan CHUNG