Abstract: A multi-chip package structure is provided, including a substrate having a grounding structure; two semiconductor elements disposed on and electrically connected to the substrate; an encapsulant formed on the substrate and encapsulating semiconductor elements, wherein the encapsulant has a plurality of round holes formed between the semiconductor elements; and an electromagnetic shielding structure formed in each of the round holes and connected to the grounding structure to achieve electromagnetic shielding effects. A method for forming the multi-chip package is also provided.

Abstract: A package structure is disclosed, which includes: a carrier having a recessed portion formed on a lower side thereof and filled with a dielectric material; a semiconductor element disposed on an upper side of the carrier and electrically connected to the carrier; and an encapsulant formed on the upper side of the carrier for encapsulating the semiconductor element. Therein, the dielectric material is exposed from the encapsulant. As such, when the carrier is disposed on a circuit board, the dielectric material is sandwiched between the lower side of the carrier and the circuit board to form a decoupling capacitor, thereby improving the power integrity.

Abstract: A semiconductor element is provided, including: a substrate having a plurality of first conductive through holes and second conductive through holes formed therein; a redistribution layer formed on the substrate and having a plurality of conductive pads electrically connected to the first conductive through holes; and a metal layer formed on the redistribution layer and electrically connected to the second conductive through holes. The metal layer further has a plurality of openings for the conductive pads of the redistribution layer to be exposed from the openings without electrically connecting the first metal layer. As such, the metal layer and the second conductive through holes form a shielding structure that can prevent passage of electromagnetic waves into or out of the redistribution layer or side surfaces of the semiconductor element, thereby effectively shield electromagnetic interference.

Abstract: A control method for bidirectional DC-DC converter includes: operating a bidirectional DC-DC converter in a boost mode, the bidirectional DC-DC converter including a low voltage side and a high voltage side, the low voltage side including low-voltage-side switches, a voltage clamping switch and a voltage clamping capacitor and the high voltage side including high-voltage-side switches; switching the voltage clamping switch with a predetermined duty cycle prior to switching on all of the low-voltage-side switches; adjusting the duty cycle of the voltage clamping switch being smaller than a turn-off interval of the low-voltage-side switches to reduce the conduction loss of the low-voltage-side switches and the voltage clamping switch; alternatively, operating the DC-DC converter in a buck mode; adjusting and extending the duty cycle of the low-voltage-side switches to overlap a turn-off time of the high-voltage-side switches so as to reduce the conduction loss of the low-voltage-side switches.

Abstract: An electrical interconnection structure includes: a signal transmission structure having a first through silicon via (TSV) and signal circuits connected to two opposite ends of the first TSV, respectively; and a grounding structure having a second TSV and grounding layers connected to two opposite ends of the second TSV, respectively. The grounding layers surround the signal circuits along the pathways thereof such that the ends of the first TSV are surrounded by the grounding layers with gaps therebetween. By changing the gaps between the grounding layers and the ends of the first TSV, the capacitance between the grounding layers and the signal circuits is adjusted so as to regulate the impedance therebetween.

Abstract: A five-level DC-AC converter includes a capacitor set and a full-bridge circuit. The capacitor set contains two DC capacitors, a power electronic switch and two diodes. When the power electronic switch is turned on/off, the two DC capacitors are connected in series/parallel to provide a two-level DC voltage to the full-bridge circuit. The full-bridge circuit further converts the two-level DC voltage to output a voltage with three voltage levels in the positive half cycle and three voltage levels in the negative half cycle. This achieves the goal of using five power electronic switches to convert DC power into AC power with five voltage levels.

Abstract: An estimation method for residual discharging time of batteries includes the steps of: providing a set of battery-discharge-current intervals and a set of battery-discharge equations, setting discharge time of each battery-discharge-current intervals zero; detecting a discharge current, voltage and time of batteries; judging whether the discharge current exceeding all of the battery-discharge-current intervals; selecting one of the battery-discharge-current intervals and the associated battery-discharge equation according to the detected discharge current; calculating an estimation of residual discharging time; accumulating and recording the discharge time; judging whether the discharge voltage being lower than a predetermined value and calculating an estimation error of the residual discharging time; adjusting parameters of the battery-discharge equation for reducing the estimation error of the residual discharging time if the estimation error is greater than a predetermined error value.

Abstract: An islanding detection apparatus for a distributed generation power system and a detection method therefor operates a power converter to act as a virtual capacitor or inductor at a frequency close to but unequal to that of a utility power system under abnormal condition of the utility power system. When power failure occurs in the utility power system, only the distributed generation power system supplies power to a load so that a load voltage has been changed in at least one of amplitude and frequency which can be immediately detected islanding phenomenon.

Abstract: A semiconductor package substrate is provided, which includes a substrate body having a plurality of conductive through holes formed therein, wherein at least two adjacent conductive through holes are formed as a differential pair, each of which has a ball pad formed at an end thereof; and at least one electrically integrated layer formed in the substrate body, and having an opening corresponding to the two adjacent conductive through holes formed as the differential pair and the ball pads thereof. Thus, the spacing between the conductive through holes and the electrically integrated layer and the spacing between the ball pads can be enlarged by the opening, so as to balance the impedance match.

Abstract: A maximum power point tracking method, applied to a tracking device, employs a DC/DC converter connecting with a solar cell array, and including a controller actuating the DC/DC converter to perform an active resistance characteristic; a maximum power point tracking circuit adjusting the active resistance of the DC/DC converter; monitoring a change of an output power of the solar cell array in determining a direction for adjusting the active resistance of the DC/DC converter; and the maximum power point tracking circuit repeatedly adjusting the active resistance of the DC/DC converter. If the change of the output power of the solar cell array is positive, the active resistance of the DC/DC converter is adjusted in the same direction; but, conversely, if the change of the output power of the solar cell array is negative, the active resistance of the DC/DC converter is adjusted in an opposite direction.

Abstract: A high electrical performance semiconductor package is proposed. A carrier is provided having a first surface, an opposite second surface, and conductive vias for electrically connecting the first surface to the second surface. A chip is attached to the first surface of the carrier. A plurality of via lands are disposed peripherally on the first surface of the carrier and electrically connected to the vias. A plurality of conductive regions are disposed on the second surface of the carrier and electrically connected to the vias. A plurality of fingers are disposed around the chip and electrically connected to the via lands by conductive traces formed on the first surface of the carrier. A plurality of bonding wires electrically connect the chip to the fingers. Lengths of the wires for transmitting differential pair signals are substantially equal, and lengths of the traces for transmitting the differential pair signals are substantially equal.

Abstract: A maximum power point tracking method, applied to a tracking device, employs a DC/DC converter connecting with a solar cell array, and including a controller actuating the DC/DC converter to perform an active resistance characteristic; a maximum power point tracking circuit adjusting the active resistance of the DC/DC converter; monitoring a change of an output power of the solar cell array in determining a direction for adjusting the active resistance of the DC/DC converter; and the maximum power point tracking circuit repeatedly adjusting the active resistance of the DC/DC converter. If the change of the output power of the solar cell array is positive, the active resistance of the DC/DC converter is adjusted in the same direction; but, conversely, if the change of the output power of the solar cell array is negative, the active resistance of the DC/DC converter is adjusted in an opposite direction.

Abstract: A semiconductor package substrate is provided, which includes a substrate body having a plurality of conductive through holes formed therein, wherein at least two adjacent conductive through holes are formed as a differential pair, each of which has a ball pad formed at an end thereof; and at least one electrically integrated layer formed in the substrate body, and having an opening corresponding to the two adjacent conductive through holes formed as the differential pair and the ball pads thereof. Thus, the spacing between the conductive through holes and the electrically integrated layer and the spacing between the ball pads can be enlarged by the opening, so as to balance the impedance match.

Abstract: An islanding detection apparatus for a distributed generation power system and a detection method therefor operates a power converter to act as a virtual capacitor or inductor at a frequency close to but unequal to that of a utility power system under abnormal condition of the utility power system. When power failure occurs in the utility power system, only the distributed generation power system supplies power to a load so that a load voltage has been changed in at least one of amplitude and frequency which can be immediately detected islanding phenomenon.

Abstract: A high electrical performance semiconductor package is proposed. A carrier is provided having a first surface, an opposite second surface, and conductive vias for electrically connecting the first surface to the second surface. A chip is attached to the first surface of the carrier. A plurality of via lands are disposed peripherally on the first surface of the carrier and electrically connected to the vias. A plurality of conductive regions are disposed on the second surface of the carrier and electrically connected to the vias. A plurality of fingers are disposed around the chip and electrically connected to the via lands by conductive traces formed on the first surface of the carrier. A plurality of bonding wires electrically connect the chip to the fingers. Lengths of the wires for transmitting differential pair signals are substantially equal, and lengths of the traces for transmitting the differential pair signals are substantially equal.

Abstract: A cavity-down ball grid array (CDBGA) semiconductor package with a heat spreader is provided, in which a substrate is formed with at least a ground ring, a plurality of ground vias, a ground layer, and at least an opening for receiving at least a chip. The substrate is mounted in a cavity of the heat spreader, and an electrically conductive adhesive is disposed between an inner wall of the cavity and edges of the substrate, so as to allow the ground layer and the ground ring exposed to the edges of the substrate to be electrically connected to the heat spreader by means of the electrically conductive adhesive. By the above arrangement with the heat spreader being included in a grounding circuit path of the chip, ground floatation and excess ground inductance and resistance can be prevented for the semiconductor package, thereby solving heat-dissipation, electromagnetic interference and crosstalk problems.

Abstract: A cavity-down ball grid array (CDBGA) semiconductor package with a heat spreader is provided, in which a substrate is formed with at least a ground ring, a plurality of ground vias, a ground layer, and at least an opening for receiving at least a chip. The substrate is mounted in a cavity of the heat spreader, and an electrically conductive adhesive is disposed between an inner wall of the cavity and edges of the substrate, so as to allow the ground layer and the ground ring exposed to the edges of the substrate to be electrically connected to the heat spreader by means of the electrically conductive adhesive. By the above arrangement with the heat spreader being included in a grounding circuit path of the chip, ground floatation and excess ground inductance and resistance can be prevented for the semiconductor package, thereby solving heat-dissipation, electromagnetic interference and crosstalk problems.