Abstract: A method of the measuring a critical dimension of a spacer is provided. The measurement is performed by using several test structures of measuring doping region resistance. Each of the test structure has different space disposed between a first gate line and a second gate line. By measuring a doping region resistance of each test structure, a plot of reciprocal of resistance versus space can be accomplished. Then, making regression of the plot, a correlation can be formed. Finally, a critical dimension of a spacer can be get by extrapolating the correlation back to 0 unit of reciprocal of resistance.

Abstract: A semiconductor layout structure and a testing method thereof are disclosed. The semiconductor layout structure includes a device under test (DUT), a first testing pad, a second testing pad and a plurality of third testing pads. The DUT includes a plurality of metal-oxide-semiconductor (MOS) transistors. Each of the MOS transistors includes a first terminal, a second terminal and a third terminal. The first testing pad is coupled to the first terminals for being applied a first voltage. The second testing pad is coupled to the second terminals for being applied a second voltage. The third testing pads are respectively coupled to the third testing pads for being applied a third voltage. The third testing pads are electrical insulated from each other. The third voltage is larger than the first voltage and the second voltage.

Abstract: A layout structure of an electronic element comprising an electronic matrix, a first load and a second load is disclosed. The first load couples to a first end of the electronic matrix and comprises a first testing pad and a second testing pad coupling to the first testing pad. The second load couples to a second end of the electronic matrix and comprises a third testing pad and a fourth testing pad coupling to the third testing pad.

Abstract: A method of electrical device characterization comprises: providing an array of electrical devices arranged in rows and columns, wherein each electrical device has a first terminal, a second terminal and a third terminal; clamping a first voltage at a first terminal of a selected electrical device via a first buffer or an first external voltage source; clamping a second voltage at a second terminal of a selected electrical device via a second buffer or a second external voltage source; controlling a third buffer to couple the third terminal of the selected electrical device to a first terminal or a second terminal of at least one non-selected column of electrical devices; and deriving a characterization result via the third terminal of the selected electrical device; wherein the array of electrical devices, the first buffer, the second buffer and the third buffer are on a same die or a same module.

Abstract: A method for predicting tolerable contact-to-gate spacing is provided. At first, a wafer with a plurality of source/drain contacts are provided. Then, a plurality of testing gate lines are formed on the wafer by using a photomask. In one die, there are different contact-to-gate distances ranging from d+?d to d??d wherein d is the standard spacing and ?d<d. Then, the wafer is inspected to find failure counts corresponding to each contact-to-gate distance. The tolerable spacing is determined according to the failure counts and the contact-to-gate distances based on a statistical method.

Abstract: A method of electrical device characterization comprises: providing an array of electrical devices arranged in rows and columns, wherein each electrical device has a first terminal, a second terminal and a third terminal; clamping a first voltage at a first terminal of a selected electrical device via a first buffer or an first external voltage source; clamping a second voltage at a second terminal of a selected electrical device via a second buffer or a second external voltage source; controlling a third buffer to couple the third terminal of the selected electrical device to a first terminal or a second terminal of at least one non-selected column of electrical devices; and deriving a characterization result via the third terminal of the selected electrical device; wherein the array of electrical devices, the first buffer, the second buffer and the third buffer are on a same die or a same module.

Abstract: A method for predicting tolerable contact-to-gate spacing is provided. At first, a wafer with a plurality of source/drain contacts are provided. Then, a plurality of testing gate lines are formed on the wafer by using a photomask. In one die, there are different contact-to-gate distances ranging from d+?d to d??d wherein d is the standard spacing and ?d<d. Then, the wafer is inspected to find failure counts corresponding to each contact-to-gate distance. The tolerable spacing is determined according to the failure counts and the contact-to-gate distances based on a statistical method.

Abstract: A connector structure includes an insulating body defining a plurality of connector housings integrally combined each with the other within the insulating body, a plurality of conducting terminals, and a seat removably secured at one end of the insulating body. Each connector housing has a plurality of respective channels, while the seat is provided with first and second terminal grooves extending at respective areas of the seat. Conducting terminals of each connector are installed in the insulating body with connector portions of the conducting terminals extending through channels of a respective connector and with the tail portions of the conducting terminals passing through respective terminal grooves defined through the seat. The overall structure, due to the integral formation of a plurality of the connector housings within the single insulating body is simple in assembling, as well as low in manufacturing cost.