Patents by Inventor Wen Kai Lin
Wen Kai Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250105163Abstract: A semiconductor chiplet device includes a first die, a second die, a decoupling circuit and an interposer. The interposer includes a plurality of power traces and a plurality of ground traces. The first die and the second die are arranged on a first side of the interposer according to a configuration direction, and are coupled to the power traces and the ground traces. The decoupling circuit is arranged on a second side of the interposer, and is coupled to the power traces and the ground traces. The power traces and the ground traces are staggered with each other, and an extending direction of the ground traces and the power traces is the same as the configuration direction.Type: ApplicationFiled: March 20, 2024Publication date: March 27, 2025Inventors: Liang-Kai CHEN, Chih-Chiang HUNG, Wen-Yi JIAN, Yuan-Hung LIN, Sheng-Fan YANG
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Publication number: 20250089281Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate including a fin portion, first and second doped regions having a first conductive type, first and second contacts, and first and second metal silicide layers. The fin portion protrudes from a surface of the substrate. The first doped region is disposed in the fin portion. The second doped region is disposed in the fin portion and connected to the first doped region. A doping concentration of the second doped region is greater than that of the first doped region. The first contact is disposed on the first doped region. The second contact is disposed on the second doped region. The first metal silicide layer is disposed between the first contact and the first doped region. The second metal silicide layer is disposed between the second contact and the second doped region.Type: ApplicationFiled: October 15, 2023Publication date: March 13, 2025Applicant: United Microelectronics Corp.Inventors: Wen-Kai Lin, Sheng-Yuan Hsueh, Kuo-Hsing Lee, Chih-Kai Kang
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Semiconductor device including multiple inner spacers with different etch rates and method of making
Patent number: 12249639Abstract: Improved inner spacers for semiconductor devices and methods of forming the same are disclosed.Type: GrantFiled: January 2, 2024Date of Patent: March 11, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Kai Lin, Che-Hao Chang, Chi On Chui, Yung-Cheng Lu -
Publication number: 20250071983Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a transistor region and an one time programmable (OTP) capacitor region, forming a first fin-shaped structure on the transistor region and a second fin-shaped structure on the OTP capacitor region, and then performing an oxidation process to form a gate oxide layer on the first fin-shaped structure and the second fin-shaped structure. Preferably, the first fin-shaped structure and the second fin-shaped structure have different shapes under a cross-section perspective.Type: ApplicationFiled: September 24, 2023Publication date: February 27, 2025Applicant: UNITED MICROELECTRONICS CORP.Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Yung-Chen Chiu, Chih-Kai Kang, Wen-Kai Lin
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Patent number: 12229590Abstract: A content channel generation device comprises a resource unit assignment circuit, for assigning scheduled station(s) as node(s) of a full binary tree according to a search algorithm; a node computing circuit, for determining first node connection information of the full binary tree, and to determine second node connection information of a smallest full binary tree according to a smallest binary tree algorithm and the first node connection information; a load balance circuit, for determining user field numbers corresponding to content channels according to a load balance function and the second node connection information; a user field generation circuit, for generating a traversal result of the smallest full binary tree according to a traversal algorithm and the second node connection information, and for generating user fields corresponding to the content channels according to the traversal result, to generate the content channels.Type: GrantFiled: March 25, 2021Date of Patent: February 18, 2025Assignee: Realtek Semiconductor Corp.Inventors: Jhe-Yi Lin, Chun-Kai Tseng, Wen-Yung Lee, Shau-Yu Cheng
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Patent number: 12227619Abstract: The present invention provides a polyimide-based copolymer and electronic component and field effect transistor comprising the same. The polyimide-based copolymer comprises a copolymer of dianhydride and heterocyclic diamine, wherein the heterocyclic diamine has two benzene rings, and there are two ether bonds, two thioether bonds, or one ether bond and one thioether bond between the two benzene rings. The novel polyimide-based copolymer of the invention has excellent thermal-mechanical stability, has potential application prospects, and can be used as a substrate for flexible electronics.Type: GrantFiled: June 11, 2021Date of Patent: February 18, 2025Assignee: NATIONAL TAIWAN UNIVERSITYInventors: Wen-Chang Chen, Mitsuru Ueda, Chun-Kai Chen, Yan-Cheng Lin
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Patent number: 12212926Abstract: A MEMS structure is provided. The MEMS structure includes a substrate and a backplate, the substrate has an opening portion, and the backplate is disposed on one side of the substrate and has acoustic holes. The MEMS structure also includes a diaphragm disposed between the substrate and the backplate, and the diaphragm extends across the opening portion of the substrate and includes outer ventilation holes and inner ventilation holes arranged in a concentric manner. The outer ventilation holes and the inner ventilation holes are relatively arranged in a ring shape and surround the center of the diaphragm. The MEMS structure further includes a pillar disposed between the backplate and the diaphragm. The pillar prevents the diaphragm from being electrically connected to the backplate.Type: GrantFiled: October 28, 2022Date of Patent: January 28, 2025Assignee: FORTEMEDIA, INC.Inventors: Wen-Shan Lin, Chun-Kai Mao, Chih-Yuan Chen, Jien-Ming Chen, Feng-Chia Hsu, Nai-Hao Kuo
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Patent number: 12207052Abstract: A MEMS structure is provided. The MEMS structure includes a substrate having an opening portion and a backplate disposed on one side of the substrate. The MEMS structure also includes a diaphragm disposed between the substrate and the backplate. The opening portion of the substrate is under the diaphragm, and an air gap is formed between the diaphragm and the backplate. The MEMS structure further includes a pillar structure connected with the backplate and the diaphragm and a protection post structure extending from the backplate into the air gap. From a top view of the backplate, the protection post structure surrounds the pillar structure.Type: GrantFiled: October 3, 2022Date of Patent: January 21, 2025Assignee: FORTEMEDIA, INC.Inventors: Chun-Kai Mao, Chih-Yuan Chen, Feng-Chia Hsu, Jien-Ming Chen, Wen-Shan Lin, Nai-Hao Kuo
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Patent number: 12206012Abstract: A method includes performing an atomic layer deposition (ALD) process to form a dielectric layer on a wafer. The ALD process comprises an ALD cycle includes pulsing calypso ((SiCl3)2CH2), purging the calypso, pulsing ammonia, and purging the ammonia. The method further includes performing a wet anneal process on the dielectric layer, and performing a dry anneal process on the dielectric layer.Type: GrantFiled: May 28, 2021Date of Patent: January 21, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Kai Lin, Che-Hao Chang, Chi On Chui, Yung-Cheng Lu, Szu-Ying Chen
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Publication number: 20240395893Abstract: A semiconductor device includes a plurality of nanostructures extending in a first direction above a semiconductor substrate and arranged in a second direction substantially perpendicular to the first direction and a gate structure extending in a third direction perpendicular to both the first and second directions, the gate structure surrounding each of the plurality of nanostructures. Each of the plurality of nanostructures has an outer region having a composition different from a composition of an inner region of each of the plurality of the nanostructures. The gate structure includes a plurality of high-k gate dielectric layers respectively surrounding the plurality of nanostructures, a work function layer surrounding each of the plurality of high-k gate dielectric layers and a fill metal layer surrounding the work function layer.Type: ApplicationFiled: July 31, 2024Publication date: November 28, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen-Kai LIN, Shih-Chiang CHEN, Po-Shao LIN, Wei-Yang LEE, Chia-Pin LIN, Yuan-Ching PENG
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Publication number: 20240395902Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.Type: ApplicationFiled: July 31, 2024Publication date: November 28, 2024Inventors: Chien-Chih Lin, Yen-Ting Chen, Wen-Kai Lin, Szu-Chi Yang, Shih-Hao Lin, Tsung-Hung Lee, Ming-Lung Cheng
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Publication number: 20240387681Abstract: Semiconductor devices and methods of manufacture are presented in which spacers are manufactured on sidewalls of gates for semiconductor devices. In embodiments the spacers comprise a first seal, a second seal, and a contact etch stop layer, in which the first seal comprises a first shell along with a first bulk material, the second seal comprises a second shell along with a second bulk material, and the contact etch stop layer comprises a third bulk material and a second dielectric material.Type: ApplicationFiled: July 29, 2024Publication date: November 21, 2024Inventors: Wen-Kai Lin, Che-Hao Chang, Chi On Chui, Yung-Cheng Lu
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Patent number: 12142668Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.Type: GrantFiled: January 3, 2022Date of Patent: November 12, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Chih Lin, Yen-Ting Chen, Wen-Kai Lin, Szu-Chi Yang, Shih-Hao Lin, Tsung-Hung Lee, Ming-Lung Cheng
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Publication number: 20240332401Abstract: Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxidation anneal and heat anneal to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density.Type: ApplicationFiled: June 13, 2024Publication date: October 3, 2024Inventors: Li-Chi Yu, Cheng-I Chu, Chen-Fong Tsai, Yi-Rui Chen, Sen-Hong Syue, Wen-Kai Lin, Yoh-Rong Liu, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20240297237Abstract: A method of forming a semiconductor device includes: forming a dummy gate structure over a nanostructure, where the nanostructure overlies a fin that protrudes above a substrate, where the nanostructure comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the nanostructure on opposing sides of the dummy gate structure, the openings exposing end portions of the first semiconductor material and end portions of the second semiconductor material; recessing the exposed end portions of the first semiconductor material to form first sidewall recesses; filling the first sidewall recesses with a multi-layer spacer film; removing at least one sublayer of the multi-layer spacer film to form second sidewall recesses; and forming source/drain regions in the openings after removing at least one sublayer, where the source/drain regions seal the second sidewall recesses to form sealed air gaps.Type: ApplicationFiled: May 10, 2024Publication date: September 5, 2024Inventors: Wen-Kai Lin, Yung-Cheng Lu, Che-Hao Chang, Chi On Chui
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Patent number: 12080775Abstract: A semiconductor device includes a plurality of nanostructures extending in a first direction above a semiconductor substrate and arranged in a second direction substantially perpendicular to the first direction and a gate structure extending in a third direction perpendicular to both the first and second directions, the gate structure surrounding each of the plurality of nano structures. Each of the plurality of nanostructures has an outer region having a composition different from a composition of an inner region of each of the plurality of the nanostructures. The gate structure includes a plurality of high-k gate dielectric layers respectively surrounding the plurality of nanostructures, a work function layer surrounding each of the plurality of high-k gate dielectric layers and a fill metal layer surrounding the work function layer.Type: GrantFiled: August 30, 2021Date of Patent: September 3, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wen-Kai Lin, Shih-Chiang Chen, Po-Shao Lin, Wei-Yang Lee, Chia-Pin Lin, Yuan-Ching Peng
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Patent number: 12040382Abstract: Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxidation anneal and heat anneal to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density.Type: GrantFiled: May 17, 2021Date of Patent: July 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Li-Chi Yu, Cheng-I Chu, Chen-Fong Tsai, Yi-Rui Chen, Sen-Hong Syue, Wen-Kai Lin, Yoh-Rong Liu, Huicheng Chang, Yee-Chia Yeo
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Publication number: 20240194765Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.Type: ApplicationFiled: January 29, 2024Publication date: June 13, 2024Inventors: Yoh-Rong Liu, Wen-Kai Lin, Che-Hao Chang, Chi On Chui, Yung-Cheng Lu, Li-Chi Yu, Sen-Hong Syue
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Patent number: 12009407Abstract: A method of forming a semiconductor device includes: forming a dummy gate structure over a nanostructure, where the nanostructure overlies a fin that protrudes above a substrate, where the nanostructure comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the nanostructure on opposing sides of the dummy gate structure, the openings exposing end portions of the first semiconductor material and end portions of the second semiconductor material; recessing the exposed end portions of the first semiconductor material to form first sidewall recesses; filling the first sidewall recesses with a multi-layer spacer film; removing at least one sublayer of the multi-layer spacer film to form second sidewall recesses; and forming source/drain regions in the openings after removing at least one sublayer, where the source/drain regions seal the second sidewall recesses to form sealed air gaps.Type: GrantFiled: April 20, 2023Date of Patent: June 11, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Kai Lin, Yung-Cheng Lu, Che-Hao Chang, Chi On Chui
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Publication number: 20240153812Abstract: A method for fabricating a semiconductor device includes the steps of first forming a shallow trench isolation (STI) in a substrate, forming a first gate structure on the substrate and adjacent to the STI, forming a first doped region between the first gate structure and the STI, forming a second doped region between the first doped region and the first gate structure, forming a first contact plug on the first doped region, and then forming a second contact plug on the second doped region.Type: ApplicationFiled: December 4, 2022Publication date: May 9, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Wen-Kai Lin, Chi-Horn Pai, Sheng-Yuan Hsueh, Kuo-Hsing Lee, Chih-Kai Kang