Abstract: An aspheric lens includes a treatment zone through which light passes to image at the retina of eyeball and a positioning zone of non-visual area outside treatment zone. The treatment zone includes a base curve and a reverse curve formed on outside of base curve. The positioning zone includes an alignment curve and a peripheral curve located outside alignment curve. A center point is formed in center of base curve, the junction of base curve and reverse curve forms a first point of intersection, the junction of reverse curve and alignment curve forms a second point of intersection, and the junction of alignment curve and peripheral curve forms a third point of intersection. The linear distance between the center point and the cornea of the preset eyeball is between 9 ?m˜21 ?m. The linear distance between the first point of intersection and the cornea of the preset eyeball is between 89 ?m˜189 ?m.

Abstract: A semiconductor device and method for forming same. According to an embodiment. The method provides a base substrate, forms a heat dissipation substrate on the base substrate, wherein a thermal conductivity of the heat dissipation substrate is between 200 Wm?1K?1 and 1200 Wm?1K?1. This method further forms a device layer on the heat dissipation substrate, wherein the device layer comprises a transistor. The method further removes the base substrate.

Abstract: A light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer; one or multiple vias penetrating the active layer and the second semiconductor layer to expose the first semiconductor layer; a first contact layer covering the one or multiple vias; a third insulating layer including a first group of one or multiple third insulating openings on the second semiconductor layer to expose the first contact layer; a first pad on the semiconductor stack and covering the first group of one or multiple third insulating openings; and a second pad on the semiconductor stack and separated from the first pad with a distance, wherein the second pad is formed at a position other than positions of the one or multiple vias in a top view of the light-emitting device.

Abstract: The invention relates to a non-orthogonal and non-symmetric contact lens and its optical zone power distribution design method, which involves planning annular curves at predetermined positions in the central optical zone of the contact lens, then, designing the plural curvature value on the radial curves on the annular curves in the central optical zone, and then designing non-orthogonal and non-symmetric curvature changes for the relative position at the central optical zone based on the changes in plural curvature values. It can form a non-orthogonal and non-symmetric curved surface in the central optical zone, and then complete the design of the power distribution of the central optical zone of the contact lens to achieve the purpose of stabilizing the contact lens power, correcting regular and irregular astigmatism, and obtaining clear vision.

Abstract: A stable structure design of contact lens includes a central optical zone, a peripheral positioning zone surrounding said central optical zone and an edge zone surrounding said peripheral positioning zone. Rotate axially along the outside of the central optical zone, and obtain at least one preset thickness zone in sequence on the surface of the peripheral positioning zone. According to the at least one preset thickness zone, multiple predetermined thickness values are obtained in the peripheral positioning zone. According to the predetermined thickness values, the peripheral positioning zone can be made to meet the thickness of the predetermined thickness values, that is, in the peripheral positioning zone, a surface with at least one different thickness can be formed to achieve the purpose of forming a stable position and not easy to deviate when wearing the contact lens.

Abstract: A semiconductor device includes a plurality of nanostructures extending in a first direction above a semiconductor substrate and arranged in a second direction substantially perpendicular to the first direction and a gate structure extending in a third direction perpendicular to both the first and second directions, the gate structure surrounding each of the plurality of nanostructures. Each of the plurality of nanostructures has an outer region having a composition different from a composition of an inner region of each of the plurality of the nanostructures. The gate structure includes a plurality of high-k gate dielectric layers respectively surrounding the plurality of nanostructures, a work function layer surrounding each of the plurality of high-k gate dielectric layers and a fill metal layer surrounding the work function layer.

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.

Abstract: Semiconductor devices and methods of manufacture are presented in which spacers are manufactured on sidewalls of gates for semiconductor devices. In embodiments the spacers comprise a first seal, a second seal, and a contact etch stop layer, in which the first seal comprises a first shell along with a first bulk material, the second seal comprises a second shell along with a second bulk material, and the contact etch stop layer comprises a third bulk material and a second dielectric material.

Abstract: A wireless transmission method includes obtaining an MCS (modulation and coding scheme) rate and a power amplifier gain of each station in a set of stations for a multi-user (MU) transmission, generating a maximum available MCS rate according to a plurality of MCS rates of the set of stations, selecting a power amplifier gain of the MU transmission according to the maximum available MCS rate, adjusting a digital gain of each station according to the power amplifier gain of the MU transmission and the power amplifier gain of each station, adjusting a frequency domain signal of each station according to the digital gain thereof, converting a plurality of adjusted frequency domain signals of the set of stations into a time domain signal, and generating an amplified signal for the MU transmission according to the power amplifier gain of the MU transmission and the time-domain signal.

Abstract: In an embodiment, a structure includes: a semiconductor substrate; a fin extending from the semiconductor substrate; a gate stack over the fin; an epitaxial source/drain region in the fin adjacent the gate stack; and a gate spacer disposed between the epitaxial source/drain region and the gate stack, the gate spacer including a plurality of silicon oxycarbonitride layers, each of the plurality of silicon oxycarbonitride layers having a different concentration of silicon, a different concentration of oxygen, a different concentration of carbon, and a different concentration of nitrogen.

Abstract: A MEMS structure is provided. The MEMS structure includes a substrate having an opening portion and a backplate disposed on one side of the substrate. The backplate comprises a backplate conductive layer and a backplate insulating layer stacked with each other. The MEMS structure also includes a diaphragm disposed between the substrate and the backplate and extending across the opening portion of the substrate. The MEMS structure further includes a pillar structure connected with the backplate. The pillar structure comprises a pillar conductive layer and a pillar insulating layer stacked with each other.

Abstract: Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxidation anneal and heat anneal to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density.

Abstract: A wireless communication method for optimizing uplink transmission from a communication partner to a wireless communication device includes the following steps: after receiving an uplink performance estimation, determining uplink adjustment information including resource unit allocation and a target received signal strength indicator according to the uplink performance estimation; generating a target channel quality indicator (CQI) according to previous uplink sounding information and the uplink adjustment information, wherein the previous uplink sounding information indicates the characteristics of the uplink transmission; determining uplink transmission setting including a modulation and coding scheme and dual carrier modulation according to the target CQI and the type of an error correction technique and transmitting a control signal to a communication partner according to the uplink transmission setting; and updating the uplink performance estimation according to a reception signal from the communication

Abstract: A MEMS structure is provided. The MEMS structure includes a substrate having an opening portion and a backplate disposed on one side of the substrate and having acoustic holes. The MEMS structure also includes a diaphragm disposed between the substrate and the backplate and extending across the opening portion of the substrate. The diaphragm includes a ventilation hole, and an air gap is formed between the diaphragm and the backplate. The MEMS structure further includes a filler structure disposed on the diaphragm, and a portion of the filler structure is disposed in the ventilation hole.

Abstract: A method of forming a semiconductor device includes: forming a dummy gate structure over a nanostructure, where the nanostructure overlies a fin that protrudes above a substrate, where the nanostructure comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the nanostructure on opposing sides of the dummy gate structure, the openings exposing end portions of the first semiconductor material and end portions of the second semiconductor material; recessing the exposed end portions of the first semiconductor material to form first sidewall recesses; filling the first sidewall recesses with a multi-layer spacer film; removing at least one sublayer of the multi-layer spacer film to form second sidewall recesses; and forming source/drain regions in the openings after removing at least one sublayer, where the source/drain regions seal the second sidewall recesses to form sealed air gaps.

Abstract: A semiconductor device includes a plurality of nanostructures extending in a first direction above a semiconductor substrate and arranged in a second direction substantially perpendicular to the first direction and a gate structure extending in a third direction perpendicular to both the first and second directions, the gate structure surrounding each of the plurality of nano structures. Each of the plurality of nanostructures has an outer region having a composition different from a composition of an inner region of each of the plurality of the nanostructures. The gate structure includes a plurality of high-k gate dielectric layers respectively surrounding the plurality of nanostructures, a work function layer surrounding each of the plurality of high-k gate dielectric layers and a fill metal layer surrounding the work function layer.

Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.

Abstract: Embodiments include nanostructure devices and methods of forming nanostructure devices which include a treatment process to expand a sidewall spacer material to close a seam in the sidewall spacer material after deposition. The treatment process includes oxidation anneal and heat anneal to expand the sidewall spacer material and crosslink the open seam to form a closed seam, lower k-value, and decrease density.