Abstract: The present invention provides a test key structure for measuring or simulating a target via array. The structure includes a substrate with a test region, a plurality of first conductive lines in the test region; a plurality of second conductive lines in the test region and on the first conductive lines, wherein the first conductive lines and the second conductive lines overlaps vertically in a plurality of target regions, and a plurality of vias disposed between the first conductive lines and the second conductive lines, wherein at least two vias vertically contact one of the first conductive lines and one of the second conductive lines.

Abstract: An intra-metal capacitor is provided. The intra-metal capacitor is formed in a dielectric layer and comprising a first electrode and a second electrode, wherein the first electrode penetrate through the whole thickness of the dielectric layer, and the second electrode does not penetrate through the whole thickness of the dielectric layer.

Abstract: An assembly apparatus (10) is provided. The assembly apparatus (10) includes a first feeding mechanism (12) arranged in use to feed a series of first components (14), a holding mechanism (16) arranged in use to hold consecutive ones of the first components (14) in place, a cutter (18) arranged in use to separate individual ones of the first components (14) while being held in place by the holding mechanism (16), an inserter (20) arranged in use to push a separated first component (14) into a corresponding opening in a second component (22), and a drive mechanism (24) coupled to each of the first feeding mechanism (12), the holding mechanism (16), the cutter (18) and the inserter (20). The drive mechanism (24) is arranged in use to synchronise movement of the first feeding mechanism (12), the holding mechanism (16), the cutter (18) and the inserter (20).