Abstract: In a method of generating an event map, a processing device obtains first information that indicates that there is an association relationship between a first event and a second event. The first information comprises association type information that indicates a type of the association relationship, and the first and second events are events in a map. The processing device then stores the first information as data of the map.

Abstract: Generating first map information, where the first map information includes information about a first reference object set, and the information about the first reference object set indicates a first identifier, in a geographic area, of each reference object in at least one reference object included in the first reference object set, and indicates a first position of each reference object in the at least one reference object. The first map information is generated, and the first map information indicates related information of each reference object in the first reference object set, to implement a manner of expressing the related information of the reference object more abundantly, so that maps provided by different map vendors may use reference objects in the first map information to perform position expression on an element or an event.

Abstract: A communication method and apparatus. A terminal device determines channel state information based on S indexes of S vectors. Each of the S vectors is included in a first vector quantization dictionary. The first vector quantization dictionary includes N1 vectors, where N1 and S are both positive integers. The terminal device sends the channel state information to a network device. Because a vector included in the vector quantization dictionary usually has a relatively large dimension, quantizing channel information by using the first vector quantization dictionary is equivalent to performing dimension expansion on the channel information or maintaining a relatively high dimension. High-precision feedback is implemented by using relatively low signaling overheads.

Abstract: An apparatus includes a plurality of switches connected in parallel between an input terminal and an output terminal of a power bus, a plurality of current sensing circuits coupled to the plurality of switches, wherein each current sensing circuit is coupled to a corresponding switch, and a plurality of current sharing circuits configured to receive current sensing signals from the plurality of current sensing circuits and generate a plurality of gate drive signals to control the plurality of switches so as to achieve a predetermined current distribution among the plurality of switches.

Abstract: A buck converter with an asymmetric threshold voltage of its gate drive circuit design for improving power efficiency while keeping the gate drive design simple.

Abstract: A food processor for processing food stuffs having a base assembly, a jar assembly, and a blade assembly that can be rotated from a use position to a stored position is disclosed. The food processor includes a lid that is connected to the jar assembly by a hinge and closed by use of a latch. The jar assembly is connected to the base assembly by the use of push pins on the base assembly which engage corresponding holes on the jar assembly.

Abstract: A method and system for fabricating a three-dimensional power module packaging structure is provided. The power module packaging method incorporates a one-time SMD-molding process, which simultaneously connects bare semiconductor dies and conductive pillars to the PCB substrate directly.

Abstract: A multiphase buck converter that includes smart two-phase power stages for reducing switching losses. Each of the smart power stages includes a first high side switch, a second high side switch, a first low side switch, a second low side switch, a switching capacitor, a first inductor, and a second inductor. The exemplary multiphase buck converter includes two such smart power stages and a multiphase controller for generating PWM signals for driving the two smart power stages synchronously.

Abstract: A circuit for a multi-phase power regulator including a power stage with a first phase and a second phase, the circuit including phase management circuitry coupled to the first phase and the second phase to control the first phase and the second phase, a first comparator coupled to an output of the multi-phase power regulator to compare a value of the output of the multi-phase power regulator to a first threshold value to produce a first comparison result, and phase shedding circuitry coupled to the first comparator and the phase management circuitry to control the phase management circuitry to activate or deactivate the second phase based at least partially on the first comparison result.

Abstract: A method for boosting light load efficiency for multiphase converters through disabling at least partially a current sense circuit, disabling partial equivalent elements of one of power stages, using small size equivalent element for one of power stages, and through utilizing higher inductance, compared to other regular phases, to reduce RMS current.

Abstract: A voltage regulator system includes a switch system including a power switch to conduct an output current through an inductor based on an input voltage and a switching signal to generate an output voltage at a load. A feedback system generates a PWM signal based on the output voltage and based on a variable reference voltage. A gate driver system generates the switching signal based on the PWM signal. The gate driver system controls the switch system to increase the output voltage at output voltage slopes in each of startup stages during startup of the voltage regulator system. A sampling system samples the output current and the output voltage during the startup of the voltage regulator system to measure each slope of the output voltage slopes at each of the respective startup stages during the startup of the voltage regulator system.