Abstract: A plant cultivation device includes: a planting container having an accommodation space; a planting pan disposed in the accommodation space of the planting container for dividing the accommodation space into a leaf region and a root region; an atomizing sheet disposed in a bottom plate of the planting container, used for performing spraying to the root region of the planting container; and a control circuit board, electrically connected to the atomizing sheet, used for controlling whether the atomizing sheet performs spraying, a nutrient solution tank, used for accommodating a nutrient solution; and a water absorbing material, wherein an end of the water absorbing material is disposed in the nutrient solution tank for taking the nutrient solution of the nutrient solution tank, and the other end of the water absorbing material is in contact with the atomizing sheet.

Abstract: A plant cultivation device includes: a planting container having an accommodation space; a planting pan disposed in the accommodation space of the planting container for dividing the accommodation space into a leaf region and a root region; an atomizing sheet disposed in a bottom plate of the planting container, used for performing spraying to the root region of the planting container; and a control circuit board, electrically connected to the atomizing sheet, used for controlling whether the atomizing sheet performs spraying, a nutrient solution tank, used for accommodating a nutrient solution; and a water absorbing material, wherein an end of the water absorbing material is disposed in the nutrient solution tank for taking the nutrient solution of the nutrient solution tank, and the other end of the water absorbing material is in contact with the atomizing sheet.

Abstract: A Schottky diode with high antistatic capability has an N? type doped drift layer formed on an N+ type doped layer. The N? type doped drift layer has a surface formed with a protection ring. Inside the protection ring is a P-type doped area. The N? type doped drift layer surface is further formed with an oxide layer and a metal layer. The contact region between the metal layer and the N? type doped drift layer and the P-type doped area forms a Schottky contact. The P-type doped area has a low-concentration lower layer and a high-concentration upper layer, so that the surface ion concentration is high in the P-type doped area. The Schottky diode thus has such advantages of lowered forward voltage drop and high antistatic capability.

Abstract: A Schottky diode with high antistatic capability has an N? type doped drift layer formed on an N+ type doped layer. The N? type doped drift layer has a surface formed with a protection ring. Inside the protection ring is a P-type doped area. The N? type doped drift layer surface is further formed with an oxide layer and a metal layer. The contact region between the metal layer and the N? type doped drift layer and the P-type doped area forms a Schottky contact. The P-type doped area has a low-concentration lower layer and a high-concentration upper layer, so that the surface ion concentration is high in the P-type doped area. The Schottky diode thus has such advantages of lowered forward voltage drop and high antistatic capability.

Abstract: A semiconductor structure and a process thereof are provided. The semiconductor structure includes a semiconductor wafer having a first surface and a second surface opposite to the first surface, through silicon vias and a crack stopping slot. The through silicon vias are embedded in the semiconductor wafer and connected between the first surface and the second surface. The crack stopping slot is located in the periphery of the second surface of the semiconductor wafer. The depth of the crack stopping slot is less than or equal to the thickness of the semiconductor wafer. The process firstly provides a semiconductor wafer having through silicon vias. Then, the aforementioned crack stopping slot is formed at a back side of the semiconductor wafer opposite to the first surface. Next, the semiconductor wafer is thinned from the back side to expose a second end of each through silicon via.

Abstract: An integrated circuit structure comprises a semiconductor substrate, a device region positioned in the semiconductor substrate, an insulating region adjacent to the device region, an isolation structure positioned in the insulating region and including a bottle portion and a neck portion filled with a dielectric material, and a dielectric layer sandwiched between the device region and the insulation region.

Abstract: A method of making planar-type bottom electrode for semiconductor device is disclosed. A sacrificial layer structure is formed on a substrate. Multiple first trenches are defined in the sacrificial layer structure, wherein those first trenches are arranged in a first direction. The first trenches are filled with insulating material to form an insulating layer in each first trench. Multiple second trenches are defined in the sacrificial layer structure between the insulating layers, and are arranged in a second direction such that the second trenches intersect the first trenches. The second trenches are filled with bottom electrode material to form a bottom electrode layer in each second trench. The insulating layers separate respectively the bottom electrode layers apart from each other. Lastly, removing the sacrificial layer structure defines a receiving space by two adjacent insulating layers and two adjacent bottom electrode layers.

Abstract: A recessed channel transistor comprises a semiconductor substrate having a trench isolation structure, a gate structure having a lower block in the semiconductor substrate and an upper block on the semiconductor substrate, two doped regions positioned at two sides of the upper block and above the lower block, and an insulation spacer positioned at a sidewall of the upper block and having a bottom end sandwiched between the upper block and the doped regions. In particular, the two doped regions serves as the source and drain regions, respectively, and the lower block of the gate structure serves as the recessed gate of the recessed channel transistor.

Abstract: An integrated circuit structure comprises a semiconductor substrate, a device region positioned in the semiconductor substrate, an insulating region adjacent to the device region, an isolation structure positioned in the insulating region and including a bottle portion and a neck portion filled with a dielectric material, and a dielectric layer sandwiched between the device region and the insulation region.

Abstract: A recessed channel transistor comprises a semiconductor substrate having a trench isolation structure, a gate structure having a lower block in the semiconductor substrate and an upper block on the semiconductor substrate, two doped regions positioned at two sides of the upper block and above the lower block, and an insulation spacer positioned at a sidewall of the upper block and having a bottom end sandwiched between the upper block and the doped regions. In particular, the two doped regions serves as the source and drain regions, respectively, and the lower block of the gate structure serves as the recessed gate of the recessed channel transistor.

Abstract: An atomic layer deposition apparatus comprises a reaction chamber, a heater configured to heat a semiconductor wafer positioned on the heater, an oxidant supply configured to deliver oxidant-containing precursors having different oxidant concentrations to the reaction chamber, and a metal supply configured to deliver a metal-containing precursor to the reaction chamber. The present application also discloses a method for preparing a dielectric structure comprising the steps of placing a substrate in a reaction chamber, performing a first atomic layer deposition process including feeding an oxidant-containing precursor having a relatively lower oxidant concentration and a metal-containing precursor to form an thinner interfacial layer on the substrate, and performing a second atomic layer deposition process including feeding the oxidant-containing precursor having an oxidant concentration higher than that used to grow the first metal oxide layer and the metal-containing precursor into the reaction chamber.

Abstract: A method for forming a trench isolation structure and a semiconductor device are provided. The method comprises the following steps: forming a patterned mask on a semiconductor substrate; defining a trench with a predetermined depth D by using the patterned mask, wherein the trench has a bottom and a side wall; forming a liner layer covering the bottom and the side wall of the trench; substantially filling the trench with a flowable oxide from the bottom to a thickness d1 to form an oxide layer; forming a barrier layer with a thickness d? to cover and completely seal the surface of the oxide layer, wherein d?<d1 and d1+d??1/2D; forming an insulating layer to fill the trench; and conducting a planarization process wherein the patterned mask is used as a stop layer. In the semiconductor substrate, the oxide layer, essentially composed of the flowable oxide, is confined in an isolated region.

Abstract: A method for forming micro-patterns is disclosed. The method forms a sacrificial layer and a mask layer. A plurality of first taper trenches is formed in the sacrificial layer. A photoresist layer is filled in the plurality of first taper trenches. The photoresist layer is used as a mask and a plurality of second taper trenches is formed in the sacrificial layer. Then, the photoresist layer is stripped to be capable of patterning a layer by the first taper trenches and the second taper trenches in the sacrificial layer. Therefore, a patterned sacrificial layer duplicating the line density by double etching is formed.

Abstract: A fabricating method for silicon on insulator is disclosed, and the fabricating method includes stripping the oxide and the nitride on the bottom surface of each of the trenches, forming a porous silicon on portions of the substrate by an anodizing process, spin coating a dielectric material to fill up the trenches and performing a thermal process to convert the porous silicon to an insulating layer.

Abstract: A method of making planar-type bottom electrode for semiconductor device is disclosed. A sacrificial layer structure is formed on a substrate. Multiple first trenches are defined in the sacrificial layer structure, wherein those first trenches are arranged in a first direction. The first trenches are filled with insulating material to form an insulating layer in each first trench. Multiple second trenches are defined in the sacrificial layer structure between the insulating layers, and are arranged in a second direction such that the second trenches intersect the first trenches. The second trenches are filled with bottom electrode material to form a bottom electrode layer in each second trench. The insulating layers separate respectively the bottom electrode layers apart from each other. Lastly, removing the sacrificial layer structure defines a receiving space by two adjacent insulating layers and two adjacent bottom electrode layers.

Abstract: An isolation method of active area for semiconductor forms an isolated active area in a substrate. The substrate is a p-type silicon substrate. A pad oxide layer is formed on the substrate. A patterned sacrificial layer and an upper mask layer are formed on the pad oxide layer, where the upper mask layer is formed over the isolation region of the substrate. A gap is formed between the patterned sacrificial layer and the upper mask layer. An implantation process is performed to dope ions into the substrate through the gap, which forms an n-type barrier to surround the active areas. Lastly, the patterned sacrificial layer is stripped, and an anodization process is utilized to convert p-type bulk silicon into porous silicon. Then, an oxidation process is performed to oxidize the porous silicon to form a silicon dioxide isolation region for the active areas.

Abstract: Capacitors and methods for fabricating the same are provided. An exemplary embodiment of a capacitor comprises a dielectric layer and a first conductive layer thereover. A supporting rib is embedded in the first conductive layer and extends along a first direction. A second conductive layer is embedded in the first conductive layer and extends along a second direction perpendicular with the first direction, wherein a portion of the second conductive layer forms across the supporting rib and is structurally supported by the supporting rib. A capacitor layer is formed between the first and second conductive layers to electrically insulate the first and second conductive layers.

Abstract: A real-time system adapted to a PVD apparatus for monitoring and controlling film uniformity is described. The system includes a shielding plate, a monitoring device, and a data processing program. The shielding plate is disposed on an inner wall of a reaction chamber above a wafer stage. An opening in the center of the shielding plate exposes the wafer. The monitoring device including a scanner and a sensor respectively disposed on opposite sidewalls of the reaction chamber between the shielding plate and the wafer stage is used for measuring the flux of the particles on every portion of the wafer to acquire real-time uniformity data including a function of the wafer position and the flux. The data processing program compares the real-time uniformity data and reference uniformity data, and a feedback signal is outputted to the PVD apparatus to adjust the process parameter thereof for controlling film uniformity.

Abstract: An integrated circuit device comprises a substrate, a stack structure including circuit structure having conductive lines positioned on the substrate, a reinforcement structure including at least one supporting member positioned on the substrate and a roof covering the circuit structure and the supporting member and at least one bonding pad positioned on the roof and electrically connected to the conductive lines. A method for preparing an integrated circuit device comprises forming a stack structure including circuit structure having conductive lines on a substrate, forming a reinforcement structure including at least one supporting member on the substrate and a roof covering the supporting member and the circuit structure and forming at least one bonding pad on the roof and electrically connecting to the conductive lines.

Abstract: An integrated circuit device comprises a substrate, a stack structure including circuit structure having conductive lines positioned on the substrate, a reinforcement structure including at least one supporting member positioned on the substrate and a roof covering the circuit structure and the supporting member and at least one bonding pad positioned on the roof and electrically connected to the conductive lines. A method for preparing an integrated circuit device comprises forming a stack structure including circuit structure having conductive lines on a substrate, forming a reinforcement structure including at least one supporting member on the substrate and a roof covering the supporting member and the circuit structure and forming at least one bonding pad on the roof and electrically connecting to the conductive lines.