Patents by Inventor Wen-Liang Huang

Wen-Liang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250046720
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a device layer, and a metallization structure. The substrate has a first surface. The device layer is over the first surface of the substrate. The device layer includes a plurality of passive component units. The metallization structure is over the device layer. The metallization structure includes a conductive bridge portion electrically connecting two adjacent passive component units.
    Type: Application
    Filed: August 1, 2023
    Publication date: February 6, 2025
    Inventors: WEN-LIANG CHEN, CHUNG-CHIANG HUANG, YING-CHUN LIN, YEN-JUN LI
  • Publication number: 20240387239
    Abstract: A manufacturing method of a semiconductor structure includes the following steps. Fin-shaped structures are formed by patterning a first region of a semiconductor substrate. A first shallow trench is formed in a second region of the semiconductor substrate. A part of the semiconductor substrate is exposed by a bottom of the first shallow trench. A first etching process is performed. At least a part of one of the fin-shaped structures is removed by the first etching process, and the part of the semiconductor substrate exposed by the first shallow trench is partially removed by the first etching process for forming a first deep trench. The manufacturing method of the present invention may be used to achieve the purposes of process simplification and/or manufacturing cost reduction.
    Type: Application
    Filed: June 14, 2023
    Publication date: November 21, 2024
    Inventors: Po-Tsang Chen, Chia-Ching Lin, Wen-Liang Huang
  • Patent number: 12148675
    Abstract: The present invention includes a chip, a plastic film layer, and an electroplated layer. A front side and a back side of the chip each comprises a signal contact. The plastic film layer covers the chip and includes a first via and a second via. The first via is formed adjacent to the chip, and the second via is formed extending to the signal contact of the front side. A conductive layer is added in the first and the second via. The conductive layer in the second via is electrically connected to the signal contact of the front side. Through the electroplated layer, the signal contact on the back side is electrically connected to the conductive layer in the first via. The conductive layer protrudes from the plastic film layer as conductive terminals. The present invention achieves electrical connection of the chip without using expensive die bonding materials.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: November 19, 2024
    Assignee: Panjit International Inc.
    Inventors: Chung-Hsiung Ho, Wei-Ming Hung, Wen-Liang Huang, Shun-Chi Shen, Chien-Chun Wang, Chi-Hsueh Li
  • Publication number: 20240379670
    Abstract: A semiconductor device includes a substrate with a high voltage region and a low voltage region. A first deep trench isolation is disposed within the high voltage region. The first deep trench isolation includes a first deep trench and a first insulating layer filling the first deep trench. The first deep trench includes a first sidewall and a second sidewall facing the first sidewall. The first sidewall is formed by a first plane and a second plane. The edge of the first plane connects to the edge of the second plane. The slope of the first plane is different from the slope of the second plane.
    Type: Application
    Filed: June 6, 2023
    Publication date: November 14, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ya-Ting Hu, Chih-Yi Wang, Yao-Jhan Wang, Wei-Che Chen, Kun-Szu Tseng, Yun-Yang He, Wen-Liang Huang, Lung-En Kuo, Po-Tsang Chen, Po-Chang Lin, Ying-Hsien Chen
  • Publication number: 20240355716
    Abstract: A die of the package device is covered by an encapsulation layer, a plurality of lead portions are configured on the bottom surface of the encapsulation layer, a side portion of each lead portion is also exposed on a side surface of the encapsulation layer, and thereby the package device is used as a side-wettable package device; wherein, in a process of manufacturing the package device, a conductive electroplated conducting layer is formed on the surface of the encapsulation layer, and the electroplated conducting layer is used to conduct electric power required during an electroplating process. After the electroplating process is completed, the electroplated conducting layer can be used as a heat dissipation layer for the package device. The heat dissipation layer completely covers the surface of the package device so as to increase heat dissipation area and to be attached by a heat sink.
    Type: Application
    Filed: June 30, 2023
    Publication date: October 24, 2024
    Inventors: CHUNG-HSIUNG HO, CHI-HSUEH LI, Yung-Hui WANG, WEN-LIANG HUANG
  • Publication number: 20240274484
    Abstract: A wafer-level-package device with peripheral side wall protection has a die, multiple conductive bumps, and a protection layer. The die has a top surface, a bottom surface, and a peripheral side wall. A cavity is formed on the peripheral side wall of the die and around the die. The multiple conductive bumps are mounted on at least one of the top surface and the bottom surface of the die. The protection layer covers the die, the cavity, and the multiple conductive bumps. The multiple conductive bumps are exposed from the protection layer.
    Type: Application
    Filed: March 7, 2023
    Publication date: August 15, 2024
    Inventors: CHUNG-HSIUNG HO, WEN-LIANG HUANG, JENG-SIAN WU
  • Publication number: 20240112943
    Abstract: A die suction assistance device is provided to a wafer. The wafer is diced into multiple dies, and a tape is taped on a bottom side of the wafer. The die suction assistance device includes a platform and multiple support structures mounted in the platform. Multiple air ducts are formed among adjacent support structures. When the wafer is air-tightly mounted on the platform, the wafer is supported by the support structures. When an external vacuum device vacuums air out of the platform, a vacuum environment with negative pressure is created in the air ducts. This allows the tape to partially separate from a backside of each of the dies towards the air ducts, and allows the dies to be picked up respectively by a suction nozzle with less chance of being damaged, securing integrities of dies.
    Type: Application
    Filed: November 8, 2022
    Publication date: April 4, 2024
    Applicant: PANJIT INTERNATIONAL INC.
    Inventors: Chung-Hsiung HO, Chi-Hsueh LI, Wen-Liang HUANG
  • Publication number: 20240094638
    Abstract: An optimization method for a mask pattern optical transfer includes steps as follows: First, a projection optical simulation is performed to obtain an optimal pupil configuration scheme corresponding to a virtual mask pattern. Next, a position scanning is performed to change the optimal pupil configuration scheme, so as to generate a plurality of adjusted pupil configuration schemes. A mask pattern transfer simulation is performed to obtain a plurality of pupil configuration schemes-critical dimension relationship data corresponding to the virtual mask pattern. Subsequently, an actual pupil configuration scheme suitable for an actual mask pattern is selected according to the plurality of pupil configuration schemes-critical dimension relationship data, and upon which an actual mask pattern transfer is performed.
    Type: Application
    Filed: November 9, 2022
    Publication date: March 21, 2024
    Inventors: Chun-Yi CHANG, Wen-Liang HUANG
  • Publication number: 20230288769
    Abstract: Disclosed herein is a solid polymer electrolyte membrane prepared by subjecting an oligomer-containing composition to a polymerization reaction. The oligomer-containing composition includes ethoxylated multifunctional acrylate monomer, polyether amine oligomer, and a lithium salt. An electrochromic device including an anode, a cathode, and the solid polymer electrolyte membrane is also disclosed. The solid polymer electrolyte membrane is disposed between the anode and the cathode.
    Type: Application
    Filed: September 27, 2022
    Publication date: September 14, 2023
    Applicant: Ming Chi University of Technology
    Inventors: Wen-Liang HUANG, Chun-Chen YANG
  • Publication number: 20220344228
    Abstract: The present invention includes a chip, a plastic film layer, and an electroplated layer. A front side and a back side of the chip each comprises a signal contact. The plastic film layer covers the chip and includes a first via and a second via. The first via is formed adjacent to the chip, and the second via is formed extending to the signal contact of the front side. A conductive layer is added in the first and the second via. The conductive layer in the second via is electrically connected to the signal contact of the front side. Through the electroplated layer, the signal contact on the back side is electrically connected to the conductive layer in the first via. The conductive layer protrudes from the plastic film layer as conductive terminals. The present invention achieves electrical connection of the chip without using expensive die bonding materials.
    Type: Application
    Filed: December 7, 2021
    Publication date: October 27, 2022
    Inventors: Chung-Hsiung Ho, Wei-Ming Hung, Wen-Liang Huang, Shun-Chi Shen, Chien-Chun Wang, Chi-Hsueh Li
  • Publication number: 20210387902
    Abstract: A method for making a beam splitter with photocatalytic coating is disclosed. First, a TiO2—SiO2 sol, a SiO2 sol, and an anatase TiO2 preform sol are prepared. A glass substrate having two opposite surfaces is provided. The two opposite surfaces of the glass substrate is coated with the TiO2—SiO2 sol, the SiO2 sol, and the anatase TiO2 preform sol by dip-coating, thereby forming a coated glass substrate with a multi-layer optical coating on each of the two opposite surfaces. The multi-layer optical coating comprises a TiO2—SiO2 coating, a SiO2 coating, and an anatase TiO2 preform coating. The coated glass substrate is subjected to an anneal process. The coated glass substrate is cut, thereby forming the beam splitter with photocatalytic coating.
    Type: Application
    Filed: June 11, 2020
    Publication date: December 16, 2021
    Inventors: Wen-Liang Huang, Wei-Hong Wang, Zhen-Feng Wang, Wei-Houng Chen, Pei-Feng Sheu
  • Patent number: 10916636
    Abstract: A method of forming gates includes the following steps. Dummy gates are formed on a substrate. A spacer material is deposited to conformally cover the dummy gates. A removing process is performed to remove parts of the spacer material and the dummy gates, thereby forming spacers and recesses in the spacers.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: February 9, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Tsang Chen, Wen-Liang Huang, Chun-Chi Yu
  • Publication number: 20200266285
    Abstract: A method of forming gates includes the following steps. Dummy gates are formed on a substrate. A spacer material is deposited to conformally cover the dummy gates. A removing process is performed to remove parts of the spacer material and the dummy gates, thereby forming spacers and recesses in the spacers.
    Type: Application
    Filed: February 15, 2019
    Publication date: August 20, 2020
    Inventors: Po-Tsang Chen, Wen-Liang Huang, Chun-Chi Yu
  • Publication number: 20180141854
    Abstract: The present invention provides a method of manufacturing a glass with anti-glare, strengthened, anti-microbial and anti-fingerprint capabilities. A glass substrate is provided with a target surface. Plural treatments are carried out, including: performing an anti-glare treatment upon the target surface by using a mixed acid solution; performing a strengthening treatment by using KNO3; performing an anti-microbial treatment by using a silver-containing fluid; and performing an anti-fingerprint treatment by forming a fluorocarbon siloxane layer on the target surface.
    Type: Application
    Filed: November 15, 2017
    Publication date: May 24, 2018
    Inventor: Wen-Liang Huang
  • Publication number: 20170144924
    Abstract: A method of manufacturing the glass substrate is provided. First, a glass substrate having a target surface is provided. Next, an abrasive blasting process for the target surface is performed. After the abrasive blasting process, an etching process for the target surface is performed. The present invention further provides a glass substrate having a target surface. The target surface has an average etching depth between 1 ?m and 100 ?m, a roughness (Ra) between 0.05 ?m and 1.5 ?m, and a friction below 0.4.
    Type: Application
    Filed: February 2, 2017
    Publication date: May 25, 2017
    Inventor: Wen-Liang Huang
  • Patent number: 9534803
    Abstract: An energy saving air conditioning system is disclosed which provides different air conditioning modes, including a closed-loop mode, an open-loop mode, and a partial-loop mode, for controlling the environment in a high-density apparatus room. The energy saving air conditioning system uses a cloud operating center to monitor the temperature and the moisture inside and outside the high-density apparatus room. The cloud operating system dynamically selects the air conditioning mode in such a manner that energy can be saved and the environment in the high-density apparatus room can be optimally managed.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: January 3, 2017
    Assignee: Quanta Computer Inc.
    Inventors: Chao-Jung Chen, Chien-Pang Chen, Kai-Hung Lin, Chih-Ming Chen, Wen-Liang Huang
  • Patent number: 9506965
    Abstract: An overlay mark including at least one first overlay mark and at least one second overlay mark is provided. The first overlay mark includes a plurality of first bars and a plurality of first spaces arranged alternately, and the first spaces are not constant. The second overlay mark includes a plurality of second bars and a plurality of second spaces arranged alternately, and the second spaces are constant. Besides, the second overlay mark partially overlaps with the first overlay mark.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: November 29, 2016
    Assignee: United Microelectronics Corp.
    Inventors: Kuo-Chun Huang, Chien-Hao Chen, Wen-Liang Huang
  • Patent number: 9304389
    Abstract: A photomask including first opaque patterns and second opaque patterns is provided. The first opaque patterns are distributed in a first plane defined in the photomask, while the second opaque patterns are disposed above the first opaque patterns and spaced apart from the first opaque patterns. In other words, the first opaque pattern and second opaque pattern are not distributed in the same plane.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: April 5, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Sho-Shen Lee, Wen-Liang Huang, Chang-Mao Wang, Kai-Lin Chuang
  • Patent number: 9136140
    Abstract: A patterning method is provided. First, a material layer is formed over a substrate. Thereafter, a plurality of directed self-assembly (DSA) patterns are formed on the material layer. Afterwards, a patterned photoresist layer is formed by using a single lithography process. The patterned photoresist layer covers a first portion of the DSA patterns and exposes a second portion of the DSA patterns. Further, the material layer is patterned by an etching process, using the patterned photoresist layer and the second portion of the DSA patterns as a mask.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: September 15, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Wen-Liang Huang, Chia-Hung Lin, Chun-Chi Yu
  • Publication number: 20150225283
    Abstract: A method of manufacturing the glass substrate is provided. First, a glass substrate having a target surface is provided. Next, an abrasive blasting process for the target surface is performed. After the abrasive blasting process, an etching process for the target surface is performed. The present invention further provides a glass substrate having a target surface. The target surface has an average etching depth between 1 ?m and 100 ?m, a roughness (Ra) between 0.05 ?m and 1.5 ?m, and a friction below 0.4.
    Type: Application
    Filed: February 10, 2014
    Publication date: August 13, 2015
    Applicant: HONY GLASS TECHNOLOGY CO., LTD.
    Inventor: Wen-Liang Huang