Patents by Inventor Wen-Liang Huang

Wen-Liang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11063124
    Abstract: A high-electron mobility transistor includes a substrate; a buffer layer over the substrate; a GaN channel layer over the buffer layer; a AlGaN layer over the GaN channel layer; a gate recess in the AlGaN layer; a source region and a drain region on opposite sides of the gate recess; a GaN source layer and a GaN drain layer grown on the AlGaN layer within the source region and the drain region, respectively; and a p-GaN gate layer in and on the gate recess.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: July 13, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shin-Chuan Huang, Chih-Tung Yeh, Chun-Ming Chang, Bo-Rong Chen, Wen-Jung Liao, Chun-Liang Hou
  • Patent number: 10916636
    Abstract: A method of forming gates includes the following steps. Dummy gates are formed on a substrate. A spacer material is deposited to conformally cover the dummy gates. A removing process is performed to remove parts of the spacer material and the dummy gates, thereby forming spacers and recesses in the spacers.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: February 9, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Tsang Chen, Wen-Liang Huang, Chun-Chi Yu
  • Publication number: 20200266285
    Abstract: A method of forming gates includes the following steps. Dummy gates are formed on a substrate. A spacer material is deposited to conformally cover the dummy gates. A removing process is performed to remove parts of the spacer material and the dummy gates, thereby forming spacers and recesses in the spacers.
    Type: Application
    Filed: February 15, 2019
    Publication date: August 20, 2020
    Inventors: Po-Tsang Chen, Wen-Liang Huang, Chun-Chi Yu
  • Publication number: 20180141854
    Abstract: The present invention provides a method of manufacturing a glass with anti-glare, strengthened, anti-microbial and anti-fingerprint capabilities. A glass substrate is provided with a target surface. Plural treatments are carried out, including: performing an anti-glare treatment upon the target surface by using a mixed acid solution; performing a strengthening treatment by using KNO3; performing an anti-microbial treatment by using a silver-containing fluid; and performing an anti-fingerprint treatment by forming a fluorocarbon siloxane layer on the target surface.
    Type: Application
    Filed: November 15, 2017
    Publication date: May 24, 2018
    Inventor: Wen-Liang Huang
  • Publication number: 20170144924
    Abstract: A method of manufacturing the glass substrate is provided. First, a glass substrate having a target surface is provided. Next, an abrasive blasting process for the target surface is performed. After the abrasive blasting process, an etching process for the target surface is performed. The present invention further provides a glass substrate having a target surface. The target surface has an average etching depth between 1 ?m and 100 ?m, a roughness (Ra) between 0.05 ?m and 1.5 ?m, and a friction below 0.4.
    Type: Application
    Filed: February 2, 2017
    Publication date: May 25, 2017
    Inventor: Wen-Liang Huang
  • Patent number: 9534803
    Abstract: An energy saving air conditioning system is disclosed which provides different air conditioning modes, including a closed-loop mode, an open-loop mode, and a partial-loop mode, for controlling the environment in a high-density apparatus room. The energy saving air conditioning system uses a cloud operating center to monitor the temperature and the moisture inside and outside the high-density apparatus room. The cloud operating system dynamically selects the air conditioning mode in such a manner that energy can be saved and the environment in the high-density apparatus room can be optimally managed.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: January 3, 2017
    Assignee: Quanta Computer Inc.
    Inventors: Chao-Jung Chen, Chien-Pang Chen, Kai-Hung Lin, Chih-Ming Chen, Wen-Liang Huang
  • Patent number: 9506965
    Abstract: An overlay mark including at least one first overlay mark and at least one second overlay mark is provided. The first overlay mark includes a plurality of first bars and a plurality of first spaces arranged alternately, and the first spaces are not constant. The second overlay mark includes a plurality of second bars and a plurality of second spaces arranged alternately, and the second spaces are constant. Besides, the second overlay mark partially overlaps with the first overlay mark.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: November 29, 2016
    Assignee: United Microelectronics Corp.
    Inventors: Kuo-Chun Huang, Chien-Hao Chen, Wen-Liang Huang
  • Patent number: 9304389
    Abstract: A photomask including first opaque patterns and second opaque patterns is provided. The first opaque patterns are distributed in a first plane defined in the photomask, while the second opaque patterns are disposed above the first opaque patterns and spaced apart from the first opaque patterns. In other words, the first opaque pattern and second opaque pattern are not distributed in the same plane.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: April 5, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Sho-Shen Lee, Wen-Liang Huang, Chang-Mao Wang, Kai-Lin Chuang
  • Patent number: 9136140
    Abstract: A patterning method is provided. First, a material layer is formed over a substrate. Thereafter, a plurality of directed self-assembly (DSA) patterns are formed on the material layer. Afterwards, a patterned photoresist layer is formed by using a single lithography process. The patterned photoresist layer covers a first portion of the DSA patterns and exposes a second portion of the DSA patterns. Further, the material layer is patterned by an etching process, using the patterned photoresist layer and the second portion of the DSA patterns as a mask.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: September 15, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Wen-Liang Huang, Chia-Hung Lin, Chun-Chi Yu
  • Publication number: 20150225283
    Abstract: A method of manufacturing the glass substrate is provided. First, a glass substrate having a target surface is provided. Next, an abrasive blasting process for the target surface is performed. After the abrasive blasting process, an etching process for the target surface is performed. The present invention further provides a glass substrate having a target surface. The target surface has an average etching depth between 1 ?m and 100 ?m, a roughness (Ra) between 0.05 ?m and 1.5 ?m, and a friction below 0.4.
    Type: Application
    Filed: February 10, 2014
    Publication date: August 13, 2015
    Applicant: HONY GLASS TECHNOLOGY CO., LTD.
    Inventor: Wen-Liang Huang
  • Publication number: 20150118602
    Abstract: A photomask including first opaque patterns and second opaque patterns is provided. The first opaque patterns are distributed in a first plane defined in the photomask, while the second opaque patterns are disposed above the first opaque patterns and spaced apart from the first opaque patterns. In other words, the first opaque pattern and second opaque pattern are not distributed in the same plane.
    Type: Application
    Filed: October 31, 2013
    Publication date: April 30, 2015
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: En-Chiuan Liou, Sho-Shen Lee, Wen-Liang Huang, Chang-Mao Wang, Kai-Lin Chuang
  • Publication number: 20150072532
    Abstract: A patterning method is provided. First, a material layer is formed over a substrate. Thereafter, a plurality of directed self-assembly (DSA) patterns are formed on the material layer. Afterwards, a patterned photoresist layer is formed by using a single lithography process. The patterned photoresist layer covers a first portion of the DSA patterns and exposes a second portion of the DSA patterns. Further, the material layer is patterned by an etching process, using the patterned photoresist layer and the second portion of the DSA patterns as a mask.
    Type: Application
    Filed: September 12, 2013
    Publication date: March 12, 2015
    Applicant: United Microelectronics Corp.
    Inventors: Wen-Liang Huang, Chia-Hung Lin, Chun-Chi Yu
  • Patent number: 8954919
    Abstract: A calculation method for generating a layout pattern in a photomask includes at least the following steps. A two-dimensional design layout including several geometric patterns distributed in a plane is provided to a computer system. The computer system is used to mark portions of the geometric patterns and generate at least one marked geometric pattern and at least one non-marked geometric pattern. The marked geometric pattern is then simulated and corrected by the computer system so as to generate a 3-D design layout. Through the simulation and correction, the marked geometric pattern and the non-marked geometric pattern are arranged alternately along an axis orthogonal to the plane. The 3-D design layout is outputted to a mask-making system afterwards.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: February 10, 2015
    Assignee: United Microelectronics Corp.
    Inventors: En-Chiuan Liou, Sho-Shen Lee, Wen-Liang Huang, Chang-Mao Wang, Kai-Lin Chuang, Yu-Chin Huang
  • Patent number: 8729716
    Abstract: An alignment accuracy (AA) mark is described, including N (N?3) pattern sets defined by N exposure steps respectively. The N exposure steps are performed also to a device area disposed on a wafer together with the AA mark. The i-th (i=1, 2 . . . N?1) pattern set surrounds the (i+1)-th pattern set. Each pattern set includes a 1st set of x-directional linear patterns, a 2nd set of x-directional linear patterns arranged opposite to the 1st set of x-directional linear patterns in the y-direction, a 1st set of y-directional linear patterns, and a 2nd set of y-directional linear patterns arranged opposite to the 1st set of y-directional linear patterns in the x-direction, wherein each set of x- or y-directional linear patterns include at least three separate parallel linear patterns.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: May 20, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Kai-Lin Chuang, Wen-Liang Huang, Chia-Hung Lin, Chun-Chi Yu
  • Publication number: 20140132283
    Abstract: An overlay mark including at least one first overlay mark and at least one second overlay mark is provided. The first overlay mark includes a plurality of first bars and a plurality of first spaces arranged alternately, and the first spaces are not constant. The second overlay mark includes a plurality of second bars and a plurality of second spaces arranged alternately, and the second spaces are constant. Besides, the second overlay mark partially overlaps with the first overlay mark.
    Type: Application
    Filed: November 12, 2012
    Publication date: May 15, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Chun Huang, Chien-Hao Chen, Wen-Liang Huang
  • Publication number: 20130105107
    Abstract: An energy saving air conditioning system is disclosed which provides different air conditioning modes, including a closed-loop mode, an open-loop mode, and a partial-loop mode, for controlling the environment in a high-density apparatus room. The energy saving air conditioning system uses a cloud operating center to monitor the temperature and the moisture inside and outside the high-density apparatus room. The cloud operating system dynamically selects the air conditioning mode in such a manner that energy can be saved and the environment in the high-density apparatus room can be optimally to managed.
    Type: Application
    Filed: May 24, 2012
    Publication date: May 2, 2013
    Applicant: QUANTA COMPUTER INC
    Inventors: Chao-Jung Chen, Chien-Pang Chen, Kai-Hung Lin, Chih-Ming Chen, Wen-Liang Huang
  • Publication number: 20130106000
    Abstract: An alignment accuracy (AA) mark is described, including N (N?3) pattern sets defined by N exposure steps respectively. The N exposure steps are performed also to a device area disposed on a wafer together with the AA mark. The i-th (i=1, 2 . . . N?1) pattern set surrounds the (i+1)-th pattern set. Each pattern set includes a 1st set of x-directional linear patterns, a 2nd set of x-directional linear patterns arranged opposite to the 1st set of x-directional linear patterns in the y-direction, a 1st set of y-directional linear patterns, and a 2nd set of y-directional linear patterns arranged opposite to the 1st set of y-directional linear patterns in the x-direction, wherein each set of x- or y-directional linear patterns include at least three separate parallel linear patterns.
    Type: Application
    Filed: October 31, 2011
    Publication date: May 2, 2013
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kai-Lin Chuang, Wen-Liang Huang, Chia-Hung Lin, Chun-Chi Yu
  • Patent number: 8325482
    Abstract: A cooling apparatus for server rack is disclosed, which is disposed above at least one server rack. The cooling apparatus for server rack includes a fan module disposed at a back end above the least one server rack, a heat exchanger module disposed at a front end above the least one server rack, and an air guide connecting the fan module and the heat exchanger module. A hot air exhausted from the back end of the least one server rack is extracted by the fan module and is sent to the heat exchanger module through the air guide, and the hot air is cooled by the heat exchanger module, and a cool air is exhausted from the front end of the least one server rack.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: December 4, 2012
    Assignee: Quanta Computer Inc.
    Inventors: Chao-Jung Chen, Kai-Hung Lin, Chih-Ming Chen, Wen-Liang Huang
  • Publication number: 20120084728
    Abstract: A button control system for medical touch screen and method thereof comprises a central control module, a touch signal input module, a lock time control module, a button lock module, a button unlock module and a cleanse display module, wherein the central control module determines the signal inputted by the touch signal input module, and selects to control the button lock module or the button unlock module thereby locking or unlocking a touch button; furthermore, the lock time control module is configured to set up the lock time for the touch button so as to preset the lock time of the touch button as cleansing the touch screen by the user, and after pressing down the cleanse touch button on the touch screen, it allows to control to lock or unlock other touch buttons and also to effectively prevent the occurrence of the situation where the screen button is erroneously touched as performing the cleanse process.
    Type: Application
    Filed: October 5, 2010
    Publication date: April 5, 2012
    Inventors: Wen-Liang HUANG, Hung-Pin Chen, Chao-Ming Chiu, Tsan-Chung Lee, Jui-Hung Tai
  • Publication number: 20120081853
    Abstract: A medical antibacterial full-flat touch screen comprises an antibacterial housing, an antibacterial rubber strip and an antibacterial full-flat panel, wherein a recessed edge is configured around the periphery at the bottom of the antibacterial rubber strip which recessed edge encompassing the periphery of the antibacterial full-flat panel, and a plurality of upright buckle holes are configured on the inner side of the periphery of the antibacterial full-flat panel. In addition, a groove is configured around the periphery at the top of the antibacterial rubber strip such that the antibacterial housing can be directly inserted into the groove, and a plurality of bumps configured on the inner side of the antibacterial housing can be positioned into the upright buckle holes thereby allowing the antibacterial housing and the antibacterial full-flat panel to combine together.
    Type: Application
    Filed: October 5, 2010
    Publication date: April 5, 2012
    Inventors: Wen-Liang Huang, Hung-Pin Chen, Chao-Ming Chiu, Tsan-Chung Lee, Jui-Hung Tai