Abstract: At least one differential pressure sensing device has an active surface with an active region and a back surface with a recess. Next, a sacrificial layer is formed on a surface of the active region. Then, the differential pressure sensing device is bonded and electrically coupled with a surface of a carrier that has at least one through-hole corresponding to the recess of the differential pressure sensing device. Afterwards, at least one molding compound is formed to encapsulate the carrier and differential pressure sensing device while exposing the through-hole region and an upper surface of the sacrificial layer. Then, a solvent is used to naturally decompose the sacrificial layer, such that the active region of the differential pressure sensing device is exposed to atmosphere, thereby forming a differential pressure sensing device package with the through-hole.

Abstract: At least one differential pressure sensing device has an active surface with an active region and a back surface with a recess. Next, a sacrificial layer is formed on a surface of the active region. Then, the differential pressure sensing device is bonded and electrically coupled with a surface of a carrier that has at least one through-hole corresponding to the recess of the differential pressure sensing device. Afterwards, at least one molding compound is formed to encapsulate the carrier and differential pressure sensing device while exposing the through-hole region and an upper surface of the sacrificial layer. Then, a solvent is used to naturally decompose the sacrificial layer, such that the active region of the differential pressure sensing device is exposed to atmosphere, thereby forming a differential pressure sensing device package with the through-hole.

Abstract: A package structure for a multi-chip integrated circuit (IC) is disclosed and the structure includes substrate having a position for bonding with chips for chip-bonding and having at least a hole for the passage of a gold wire in the course of wire-bonding, a first chip attached to the substrate with a chip bonding agent and being wire-bonded on the substrate and the chip bonding position being opposite to the 2nd chip with the substrate in-between, and the gold wire of the wire-bonding passed through the hole of the substrate from the substrate bonding pad at the substrate and on the same lateral side of the second chip and being connected to the pin pad of the first chip, at least a second chip being flip-chip bonded onto the substrate and the bonding position being at different sides of the bonding between the substrate and the first chip, and a package body including filler of the second chip extended to cover the hole of the substrate and the first chip and the gold wire connected to the substrate and th

Abstract: A method of wire bonding of a semiconductor device for resolving oxidation of copper bonding pad is disclosed. The method comprises the steps of exposing the copper bonding pad of a wafer which has been completed with semiconductor circuit fabrication; covering the copper bonding pad of the wafer with a protective anti-oxidization film which will be vaporized when heated; performing wire bonding directly without requiring the removal of the protective film, employing ultrasonic vibration energy, pressurizing deformation energy and heat energy in the course of bonding to vaporize the protective film so that the metal wire and the copper pad form a large area intermetallic compound layer for bonding.

Abstract: A fabrication method for solder bump pattern of rear section wafer package is disclosed and the method includes the steps of: (a) pattern-etching the wafer at a passivation layer for the positioning of the solder bump; (b) depositing the entire under bump metal layer,

Abstract: An improved structure of heat dissipation fin for prevention of glue-overflowing in semiconductor packaging includes a substrate and a chip bonding module, wherein the heat dissipation fin is a thin housing structure having a bottom flat section and the center position is provided with a protruded section, forming into a covering body to cover the chip and the bonding body, the top section of the protruded section is provided with a first stepped platform and the inner edge of the platform is further formed into bottom recess structure and the wall thereof is then formed vertically into a raised second stepped protruded ring, and the center at the inner edge of the second stepped protruded ring is formed into a top recessed face, thereby the first stepped ring platform and the second stepped ring platform urge the top face of the top edge of the mold to form into a structure to block the packaging adhesive such that the adhesive will not overflow into the center position of the heat dissipation fin.

Abstract: An open-typed multi-chip stack-packaging is disclosed and the packaging comprises a substrate having a first surface and a second surface, at least a through opening formed on the substrate, and including at least two layers of circuitry to electrically transmit signals; at least a first chip positioned on the upper section of the opening of the first surface and a plurality of protruded blocks being soldered onto the circuitry on the first surface of the substrate at the external region of the substrate for electrically connection; at least a second chip stacked onto the first chip and the second chip being connected electrically to the circuitry of the first surface with gold lines; at least a third chip positioned at the lower section of the opening of the second surface and having a size smaller than the first chip, and a plurality of protruded blocks being used to electrically bond with the center position of the first chip, and adhesive being used to fill the first chip and the third chip, and the regio

Abstract: A high heat dissipation micro-packaging body for semiconductor chip is disclosed and the body comprises lead frame having an etched recessed platform for a chip seat, the surrounding area of the platform being groove having a plurality of supporting belt connected to the lead frame; a substrate having a plurality of pins, corresponding to the position of the groove, for connection with gold lines; a chip being bonded to the chip seat of the lead frame with bonding agent, the gold lines being mounted at the predetermined electrically connection pin positions of the substrate and a pin pad so as to function as output, and heat energy evolved in the course of operation of the chip is dissipated from the chip seat via the support belt to other regions of the lead frame for dissipation.

Abstract: An improved structure of a pin platform of an integrated circuit having a pin platform body including a chip seat and a plurality of leading plates having their end portions being concentrated on the chip seat and the chip seat being connected to the pin platform body via the connection plate, characterized in that the surrounding of the chip seat is provided with a framing side, and the framing side is connected to a connection plate, and the surface of the chip seat is smaller than the connection surface of the IC to be installed, and the size of the framing side is larger than the size of the connection face of the IC. Therefore, a high performance greenery package is obtained and the ground wire of the IC can be soldered to the framing side, which provides a smooth connection and a communication.

Abstract: An improved structure of a pin platform of an integrated circuit having a pin platform body including a chip seat and a plurality of leading plates having their end portions being concentrated on the chip seat and the chip seat being connected to the pin platform body via the connection plate, characterized in that the surrounding of the chip seat is provided with a framing side, and the framing side is connected to a connection plate, and the surface of the chip seat is smaller than the connection surface of the IC to be installed, and the size of the framing side is larger than the size of the connection face of the IC. Therefore, a high performance greenery package is obtained and the ground wire of the IC can be soldered to the framing side, which provides a smooth connection and a communication.

Abstract: A semiconductor chip package with cooling arrangement includes a heat sink adapted for covering at least a semiconductor chip, characterized in that said heat sink has an inverted U-shaped cross section thereby forming a recess at an inner bottom thereof adapted for covering at least a semiconductor chip and a plurality of pins extending downwardly from a circumferential lower edge of said heat sink, each of said pins being formed with a neck, an enlarged head, and an open slot separating said neck and said enlarged head into two portions, whereby the package can rapidly remove heat from the semiconductor chip, filter noise and reduce inductance.

Abstract: A fabrication method of semiconductor packaging and the packaging element is disclosed. A layer of copper is formed on a thick heat-resistant tape and the surface of the copper layer is coated with a light sensitive photoresist. A light source passes through a pre-fabricated circuit negative being performed on the copper layer such that the photoresist is retained on the surface of the copper layer. An etching step is performed so as to obtain a copper wire with circuit diagram. After that, a wire bonding or a flip chip method is used to bind copper wire circuit with the chip. An appropriate packaging method is performed, a packaging element is obtained after the heat-resistant tape is removed.

Abstract: A method type 3D stacked IC package is disclosed. The present invention has an appropriate chip interposer (organic substrate, soft PI substrate) which is connected to the chip by flip chip method or wire bonding method. Another similar interposer and the connected chip are formed between the top face of the original interposer and the two interposers, and anisotropic conductive film/paste is employed to connect a flexible circuit board to between the first interposer and the inner side of the second interposer to form a 3-D structure. The top face of the interposer is connected to a chip to form an extended structure. Additionally, the top layer is formed as a bottom layer to provide with one or more than one similar extended structure.

Abstract: A semiconductor chip package with cooling arrangement includes a heat sink adapted for covering at least a semiconductor chip, characterized in that said heat sink has an inverted U-shaped cross section thereby forming a recess at an inner bottom thereof adapted for covering at least a semiconductor chip and a plurality of pins extending downwardly from a circumferential lower edge of said heat sink, each of said pins being formed with a neck, an enlarged head, and an open slot separating said neck and said enlarged head into two portions, whereby the package can rapidly remove heat from the semiconductor chip, filter noise and reduce inductance.

Abstract: A device for making metal bumps includes a hard conical tubular member having a vertical passage which is conical in shape and has a larger diameter at a bottom such that a lower portion of the vertical passage is larger than an upper portion of the vertical passage, whereby a metal wire is inserted into the vertical passage of the hard conical tubular member, with a lower end of the metal wire protruded downwardly out of the vertical passage, the lower end of the metal wire is melted to form a ball, the hard conical tubular member is approached to a raised platform formed on a top of a chip, and a load is applied to the metal wire and the metal wire is heated and bonded on the pad of die and ultrasonic energy is applied to deform the melted metal so as to fill up the lower portion of the vertical passage thereby forming a metal bump on the raised platform of the chip, and finally the hard conical tubular member is removed to pull off the necking position between the metal wire and a top of the metal bump the

Abstract: A device for making metal bumps includes a hard conical tubular member having a vertical conical passage at an upper portion thereof, a bell shaped chamber at a lower portion thereof which is larger than the vertical conical passage in diameter, located under and communicated with the vertical conical passage, and a circular recess which is larger than the bell shaped chamber in diameter, located under and communicated with the bell shaped chamber, thereby forming a capillary tube with a surface.

Abstract: A device for making metal bumps includes a hard conical tubular member having a vertical conical passage at an upper portion thereof, a bell shaped chamber at a lower portion thereof which is larger than the vertical conical passage in diameter, located under and communicated with the vertical conical passage, and a circular recess which is larger than the bell shaped chamber in diameter, located under and communicated with the bell shaped chamber, thereby forming a capillary tube with a surface.

Abstract: The present invention relates to a manufacturing method for multilayer high density substrate. The circuit layout of the first layer substrate of the multilayer board requires a high demand of pitch density, and therefore polyimide layer is used to make into polyimide substrate (or other high density polymeric film substrate), and combines with the non-high density multilayer board formed from second layer board (or more layer boards) made of organic substrate. In making the organic multilayer board, the adjacent surface of the first layer polyimide substrate (or high density polymeric film substrate), corresponding to appropriate solder pad position of the first layer polyimide substrate (or high density polymeric film substrate), is formed with a solder bump. Thus, when the individual layer board and the first layer substrate are combined, direct heating and compression are applied, such that the bump and the solder pad are bound and electrically connected.

Abstract: An ultra-thin film package, characterized in that polymeric film die carrier (or substrate) or polyimide (PI) die carrier (or substrate) is employed, and the leg position for die bonding is made into a recess shape to lower the thickness after bonding, and polymeric film die carrier (or substrate) or PI die carrier (or substrate) is made into a thin film shape by a fabrication technique (chemical etching or laser fabrication method), and the I/O leg position is made into a recess shape and the die is glued to the polymeric film die carrier (or substrate) or PI die carrier (or substrate) and then changed with a package material.

Abstract: A method of forming cylindrical bumps on a substrate for integrated circuits includes the steps of: forming copper circuits on a board of a substrate by means of electroplating; covering said board with a screening material; forming openings in said screening material to align with copper circuits on said board, filling pure copper or high melting point metal into said openings by electroplating to form cylindrical projections; forming a layer of solder alloy on an upper end of each of said cylindrical projections to be even with an upper surface of said screening material, and removing said screening material to leave the cylindrical bumps, whereby the engagement operation between the die and the substrate can be facilitated and the manufacture of the die can be easier.