Abstract: A dynamic random access memory (DRAM) includes a delay lock loop (DLL), a clock tree, an off-chip driver (OCD), a phase detector (PD) and a filter. The DLL receives a reference clock and updates a delay line, and then outputs a calibrated clock via the clock tree; the PD receives the calibrated clock via the clock tree and detects a phase difference between the calibrated clock and the reference clock; and the filter activates the DLL to update the delay line according the phase difference, wherein when a READ command is received, the filter increases the number of activations for the DLL to update the delay line, thereby shortening the access time of the DRAM.

Abstract: A memory apparatus and an operating method thereof are provided. The memory apparatus includes a memory, a temperature sensor and a control circuit. The temperature sensor senses a temperature of the memory and generating a temperature sensing signal. The control circuit is coupled to the memory and the temperature sensor. The control circuit performs access operation on the memory and changes a frequency of the access operation with reference of a delay curve according to the temperature sensing signal.

Abstract: A memory apparatus and a voltage control method of the memory apparatus are provided. The memory apparatus of the invention includes a synchronous circuit, a clock tree and a memory controller. The synchronous circuit receives a reference clock and generating a clock signal. The clock tree is coupled to an output end of the multiplexer and assigns the clock signal to a plurality of signal paths. The memory controller is coupled to the synchronous circuit and controls the synchronous circuit to adjust a frequency of the clock signal according to an operating mode of the memory apparatus.

Abstract: A memory apparatus and a voltage control method of the memory apparatus are provided. The memory apparatus of the invention includes a synchronous circuit, a clock tree and a memory controller. The synchronous circuit receives a reference clock and generating a clock signal. The clock tree is coupled to an output end of the multiplexer and assigns the clock signal to a plurality of signal paths. The memory controller is coupled to the synchronous circuit and controls the synchronous circuit to adjust a frequency of the clock signal according to an operating mode of the memory apparatus.

Abstract: An operating method of a memory device includes the following operations: detecting a first temperature of the memory device; determining a first refresh rate according to the first temperature; and refreshing the memory array by the first refresh rate. The first refresh rate is lower than a refresh rate upper threshold.

Abstract: A memory apparatus and an operating method thereof are provided. The memory apparatus includes a memory, a temperature sensor and a control circuit. The temperature sensor senses a temperature of the memory and generating a temperature sensing signal. The control circuit is coupled to the memory and the temperature sensor. The control circuit performs access operation on the memory and changes a frequency of the access operation with reference of a delay curve according to the temperature sensing signal.

Abstract: The present disclosure provides a frequency-adjusting circuit comprising a temperature-sensing module, a computing module and a storage module. The temperature-sensing module is configured to measure temperatures of a plurality of DRAM chips. The storage module is coupled between the temperature-sensing module and the computing module, and is configured to store the temperatures of the plurality of DRAM chips. the computing module is coupled to the temperature-sensing module and is configured to compare the temperatures of the plurality of DRAM chips measured by the temperature-sensing module to determine a first temperature, to compare previous temperatures of the plurality of DRAM chips read from the storage module to determine a second temperature, and to compare the first temperature with the second temperature to determine a refresh frequency for the plurality of DRAM chips.

Abstract: The present disclosure provides a detecting circuit. The detecting circuit includes a clock module, a clock receiver, a delay-locked loop module, a clock tree module, an off-chip driver, a pad, a phase detector, a voltage-detecting module and a control module. The clock module provides a clock signal to the clock receiver. The clock receiver sends the clock signal to the pad through the delay-locked loop module, the clock tree module and the off-chip driver. The control module is coupled to the voltage-detecting module and the delay-locked loop module. The voltage-detecting module is coupled between the control module and the clock tree module, and is configured to detect a voltage of the clock tree module and to send a voltage comparison information to the control module. The control module is configured to control a refresh frequency of the delay-locked loop module.

Abstract: The present disclosure provides a frequency-adjusting circuit comprising a temperature-sensing module, a computing module and a storage module. The temperature-sensing module is configured to measure temperatures of a plurality of DRAM chips. The storage module is coupled between the temperature-sensing module and the computing module, and is configured to store the temperatures of the plurality of DRAM chips. The computing module is coupled to the temperature-sensing module and is configured to compare the temperatures of the plurality of DRAM chips measured by the temperature-sensing module to determine a first temperature, to compare previous temperatures of the plurality of DRAM chips read from the storage module to determine a second temperature, and to compare the first temperature with the second temperature to determine a refresh frequency for the plurality of DRAM chips.

Abstract: The present disclosure provides a detecting circuit. The detecting circuit includes a clock module, a clock receiver, a delay-locked loop module, a clock tree module, an off-chip driver, a pad, a phase detector, a voltage-detecting module and a control module. The clock module provides a clock signal to the clock receiver. The clock receiver sends the clock signal to the pad through the delay-locked loop module, the clock tree module and the off-chip driver. The control module is coupled to the voltage-detecting module and the delay-locked loop module. The voltage-detecting module is coupled between the control module and the clock tree module, and is configured to detect a voltage of the clock tree module and to send a voltage comparison information to the control module. The control module is configured to control a refresh frequency of the delay-locked loop module.

Abstract: A dynamic random access memory (DRAM) includes a delay lock loop (DLL), a clock tree, an off-chip driver (OCD), a phase detector (PD) and a filter. The DLL receives a reference clock and updates a delay line, and then outputs a calibrated clock via the clock tree; the PD receives the calibrated clock via the clock tree and detects a phase difference between the calibrated clock and the reference clock; and the filter activates the DLL to update the delay line according the phase difference, wherein when a READ command is received, the filter increases the number of activations for the DLL to update the delay line, thereby shortening the access time of the DRAM.

Abstract: A circuitry includes a source circuit; a first circuit; a second circuit; and a data-distributing circuit including: a receiving circuit configured to receive a first datum for the first circuit via a first and second front line, and to receive from the source circuit a second datum for the second circuit via a third front line and a fourth front line; and a forwarding circuit configured to receive one of the first datum and the second datum via a first intermediate line and a second intermediate line, to receive a target address associated with the one of the first datum and the second datum via a third intermediate line, and, according to the target address, provide the one of the first datum and the second datum to one of the first circuit and the second circuit.

Abstract: An operating method of a clock signal generating circuit includes the following operations: transmitting a clock signal to a clock tree circuit by a voltage detector; and adjusting a frequency of the clock signal according to a voltage of the clock tree circuit so as to maintain the voltage within a voltage range.

Abstract: A circuitry includes a source circuit; a first circuit; a second circuit; and a data-distributing circuit including: a receiving circuit configured to receive a first datum for the first circuit via a first and second front line, and to receive from the source circuit a second datum for the second circuit via a third front line and a fourth front line; and a forwarding circuit configured to receive one of the first datum and the second datum via a first intermediate line and a second intermediate line, to receive a target address associated with the one of the first datum and the second datum via a third intermediate line, and, according to the target address, provide the one of the first datum and the second datum to one of the first circuit and the second circuit.

Abstract: A chip having information of a result of a chip probing test and a method for checking the results of the chip probing test are disclosed. The chip includes a chip substrate and a record module located on the chip substrate. The record module is configured to record a status code indicating whether the chip passes the chip probing test. The method includes following steps: executing the chip probing test for the chip; and recording the status code in the record module of the chip, the status code indicating whether the chip passes the chip probing test.

Abstract: An integrated circuit comprising at least one signal path which is adapted to route at least one signal from an origin to a target block, said signal path comprising at least an adjustable driver circuit comprising an input and an output, which is adapted to receive an electric signal having a first signal power as an input signal and which is adapted to provide an electric signal having a second signal power as an output signal is provided. Furthermore, the integrated circuit comprises at least one interconnect having an ohmic resistance and an electric capacity and being adapted to route said electric signal having a second signal power to said target block. Furthermore, a method for manufacturing such an integrated circuit is provided.

Abstract: The present invention provides a dynamic random access memory apparatus includes a first chip and a second chip. The first chip includes a plurality of memory cells and a plurality of through-silicon vias (TSVs). The plurality of memory cells are arranged in an array. First terminals of the TSVs are respectively coupled to the memory cells. The first chip and the second chip are overlapped, the second chip includes a plurality storage capacitors. Second terminals of the TSVs are respectively coupled to the storage capacitors storage capacitors.

Abstract: The present invention provides a dynamic random access memory apparatus includes a first chip and a second chip. The first chip includes a plurality of memory cells and a plurality of through-silicon vias (TSVs). The plurality of memory cells are arranged in an array. First terminals of the TSVs are respectively coupled to the memory cells. The first chip and the second chip are overlapped, the second chip includes a plurality storage capacitors. Second terminals of the TSVs are respectively coupled to the storage capacitors storage capacitors.

Abstract: A temperature sensing system, which comprises: a temperature analyzing circuit, for sensing temperature and generating an analyzing result in response to the sensed temperature; and a control unit, for controlling a temperature sensing time interval; wherein the control unit continuously changes the temperature sensing time interval according to a predetermined temperature range in response to the sensed temperature.