Patents by Inventor Wen (Phil) Shih CHEN

Wen (Phil) Shih CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250120230
    Abstract: An optical structure is provided. The optical structure includes a substrate, a light-emitting element, a glue layer, and a light-adjusting element. The light-emitting element is disposed on the substrate. The glue layer covers the light-emitting element. The light-adjusting element is disposed on the glue layer. Moreover, the refractive index of the glue layer is different from the refractive index of the light-adjusting element.
    Type: Application
    Filed: August 21, 2024
    Publication date: April 10, 2025
    Inventors: Shu-Ching PENG, Yu-Hsi SUNG, Jung-Cheng CHANG, Wei-Chung CHENG, Yin-Cyuan WU, Sheng-Fu WANG, Wen-Yu LEE
  • Publication number: 20250118690
    Abstract: A semiconductor package includes: a die having a conductive pad at a first side of the die; and a redistribution structure over the first side of the die and electrically coupled to the die. The redistribution structure includes: a first dielectric layer including a first dielectric material; a first via in the first dielectric layer, where the first via is electrically coupled to the conductive pad of the die; and a first dielectric structure embedded in the first dielectric layer, where the first dielectric structure includes a second dielectric material different from the first dielectric material, where the first dielectric structure laterally surrounds the first via and contacts sidewalls of the first via.
    Type: Application
    Filed: October 6, 2023
    Publication date: April 10, 2025
    Inventors: Wen-Yi Lin, Kan-Ju Yang, Kai-Cheng Chen, Chien-Li Kuo, Chien-Chen Li
  • Publication number: 20250120122
    Abstract: One aspect of the present disclosure pertains to a semiconductor device. The semiconductor device includes a semiconductor substrate and a transistor formed over the semiconductor substrate. The transistor includes a first source/drain (S/D) feature, a second S/D feature, a channel region interposed between the first and second S/D features, and a gate stack engaging the channel region. The semiconductor device includes a first S/D contact landing on a top surface of the first S/D feature, a second S/D contact landing on a top surface of the second S/D feature, and a dielectric plug penetrating through the semiconductor substrate and landing on a bottom surface of the first S/D feature. The dielectric plug spans a width equal to or smaller than a width of the first S/D feature.
    Type: Application
    Filed: October 5, 2023
    Publication date: April 10, 2025
    Inventors: Chen-Ming Lee, Shih-Chieh Wu, Po-Yu Huang, I-Wen Wu, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20250119631
    Abstract: An imaging lens module has an image surface and includes an optical lens assembly, a plurality of monomer structures and a cover member. The optical lens assembly is disposed on an object side of the image surface and defines an optical axis. The optical lens assembly includes a light-blocking element, which includes a light-blocking portion. The light-blocking portion is disposed closer to the optical axis than a portion of the light-blocking element other than the light-blocking portion thereto. The monomer structures are disposed on the object side of the image surface, and each of the monomer structures is extended along a direction parallel to the optical axis. The cover member is disposed on an object side of the optical lens assembly, and the optical axis passes through the cover member. The monomer structures are disposed on the light-blocking portion of the light-blocking element.
    Type: Application
    Filed: September 26, 2024
    Publication date: April 10, 2025
    Inventors: Chih-Wen HSU, Heng-Yi SU
  • Publication number: 20250116509
    Abstract: In one aspect, a head-wearable device includes a body with a housing and a plurality of electrical components arranged in the housing, including a logic board. The head-wearable device is detachably couplable to the housing. The front-facing outer cover includes a first set of components mounted to the front-facing outer surface, each respective component of the first set of components comprising a first set of sensors, and a second set of components mounted to the front-facing outer surface, each respective component of the second set of components comprising a second set of sensors. The head-wearable device includes a first set of flex assemblies configured to communicatively couple a respective sensor of the first set of sensors to the logic board. And the head-wearable device includes a second set of flex assemblies configured to communicatively couple respective components of the second set of second set of components to the logic board.
    Type: Application
    Filed: July 15, 2024
    Publication date: April 10, 2025
    Inventors: Vinay Arvind Iyer, Lucas Wen Tang, Reza Anvari, Ann McInroy, Celia Leach Doud, Kyle Trieu, John Terpsma
  • Publication number: 20250116257
    Abstract: The present disclosure relates to a lightning protection device, a lightning protection system, a wind power generator set, and a method. The lightning protection device includes a transition conductor with a predetermined length, width and thickness, the transition conductor comprising a first connecting end and a second connecting end opposite to each other in its length direction, the first connecting end being configured for receiving lightning current, and the second connecting end being configured for connection with a down lead system. The transition conductor includes a thinned area and an edge area, the edge area surrounds at least a portion of the thinned area, one side of the edge area and one side of the thinned area in the length direction are connected and jointly form the first connecting end, and a thickness of the thinned area is less than that of the edge area.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 10, 2025
    Inventors: Lei FU, Birong WEN, Quanzhou LI
  • Publication number: 20250116938
    Abstract: A method includes: forming a mask layer on a semiconductor wafer; forming a tin droplet, including: supplying tin to a high-pressure reservoir from a low-pressure reservoir; monitoring a level of tin in the high-pressure reservoir by at least two electrodes attached to the high-pressure reservoir; in response to the level of the tin exceeding a threshold value, supplying the tin to a droplet generator from the high-pressure reservoir; forming the tin droplet by the droplet generator using the tin supplied from the high-pressure reservoir; generating light by the tin droplet; and patterning the mask layer by the light.
    Type: Application
    Filed: October 9, 2023
    Publication date: April 10, 2025
    Inventors: Chi YANG, Po-Yuan YEH, Che-Hsin LIN, Jen Chieh YU, Chung Wen LUO
  • Publication number: 20250118560
    Abstract: A method for fabricating a semiconductor device includes steps as follows. A gate structure is formed on a substrate. A fluorine-containing dopant is implanted into the substrate to form two lightly doped drain regions at two sides of the gate structure. A thermal treatment process is performed, in which a part of fluorine atoms of the fluorine-containing dopant diffuse onto a surface of the substrate. The part of fluorine atoms are removed.
    Type: Application
    Filed: November 16, 2023
    Publication date: April 10, 2025
    Applicant: United Semiconductor (Xiamen) Co., Ltd.
    Inventors: LINSHAN YUAN, Guang Yang, Liangfeng Zhang, Jinjian OUYANG, Chin-Chun Huang, WEN YI TAN
  • Publication number: 20250118656
    Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate, a first conductive line, a first conductive via, a second conductive line, and a first barrier layer. The first conductive line is disposed on the substrate. The first conductive via is disposed on the first conductive line. The second conductive line is disposed on the first conductive line. The first barrier layer is disposed between the first conductive via and the second conductive line.
    Type: Application
    Filed: October 6, 2023
    Publication date: April 10, 2025
    Inventors: HWEI-JAY CHU, HSI-WEN TIEN, WEI-HAO LIAO, YU-TENG DAI, HSIN-CHIEH YAO, CHENG-HAO CHEN, CHIH WEI LU
  • Publication number: 20250115846
    Abstract: The invention provides an automatic stirring device in the field of fluid machinery and bioreactors, focusing on enhancing fluid control efficiency and consistency in biological cultivation processes. It utilizes a flexible channel body or reactor body to facilitate the flow of nutrient solution along specific channels (such as S-shaped flexible channels or S-shaped loop channels), designed to reduce shear forces and achieve iso-level uniform flow. A power system and monitoring and control system are employed to regulate the flow of nutrient solution and monitor cultivation conditions in real-time, thus supporting various bioprocess cultivation requirements.
    Type: Application
    Filed: October 4, 2024
    Publication date: April 10, 2025
    Inventors: Wen Quan WANG, Lei TANG, Xiu WANG, Xin Yu WEI, Yan YAN, Chao ZHANG
  • Publication number: 20250120087
    Abstract: Provided are a memory structure and a manufacturing method thereof. The memory structure includes first and second gates, a dielectric hump, a first spacer, a charge storage layer, a gate dielectric layer, a high-k layer and doped regions. The first and the second gates are disposed on a substrate. The dielectric hump is disposed on the substrate between the first gate and the second gate. The first spacer is disposed on a sidewall of the dielectric hump. The charge storage layer is disposed between the first gate and the substrate. The gate dielectric layer is disposed between the second gate and the substrate. The high-k layer is disposed between the first gate and the charge storage layer and between the second gate and the gate dielectric layer. The doped regions are disposed in the substrate at two sides of the first gate and at two sides of the second gate.
    Type: Application
    Filed: November 6, 2023
    Publication date: April 10, 2025
    Applicant: United Microelectronics Corp.
    Inventors: Jen Yang Hsueh, Chien-Hung Chen, Tzu-Ping Chen, Chia-Hui Huang, Chia-Wen Wang, Chih-Yang Hsu, Ling Hsiu Chou
  • Publication number: 20250114930
    Abstract: A high-speed nail combined with an inner-toothed tube having an expandable padding includes: a main body including a tubular member and an expandable flange, the tubular member including a first space and a threaded portion, the expandable flange integrally projecting form the tubular member and expending in a nailing direction to define a second space, the second space being in communication with the first space; a drive pin connected to the tubular member by insertion in the nailing direction, including a nail head and a nail body connected to each other, the nail head being located in the first space, the nail body extending from the first space to the second space; and a gunpowder actuating unit received in the first space.
    Type: Application
    Filed: October 6, 2023
    Publication date: April 10, 2025
    Inventor: WEN-CHANG YANG
  • Publication number: 20250116001
    Abstract: A semiconductor processing chamber may include a pedestal configured to support a substrate during a plasma-enhanced chemical-vapor deposition (PECVD) process that forms a film on a surface of the substrate. The chamber may also include one or more internal meshes embedded in the pedestal. The one or more internal meshes may be configured to deliver radio-frequency (RF) power to a plasma in the semiconductor processing chamber during the PECVD process. An outer diameter of the one or more internal meshes may be less that a diameter of the substrate. The chamber may further include an RF source configured to deliver the RF power to the one more internal meshes. This configuration may reduce arcing within the processing chamber.
    Type: Application
    Filed: October 6, 2023
    Publication date: April 10, 2025
    Applicant: Applied Materials, Inc.
    Inventors: Allison Yau, Manoj Kumar Jana, Wen-Shan Lin, Zhiling Dun, Xinhai Han, Deenesh Padhi, Jian Li, Yuanchang Chen, Wenhao Zhang, Edward P. Hammond, Alexander V. Garachtchenko, Ganesh Balasubramanian, Juan Carlos Rocha-Alvarez, Sathya Ganta
  • Publication number: 20250115536
    Abstract: A method for reducing the risk of burning and explosion in a deoxygenation process of an oxygen-containing gas includes multiple steps. According to this method, in the presence of a gaseous alkane, hydrogen reacts with an oxygen-containing gas from which an unsaturated hydrocarbon has been removed. The oxygen-containing gas contains the oxygen and the unsaturated hydrocarbon, and the content of the oxygen in the oxygen-containing gas is greater than 0.5% by volume. A gaseous alkane is introduced to reduce the risk of burning and explosion of a mixed gas. A hydrocatalytic reaction is carried out to promote oxygen in the mixed gas to react with hydrogen to produce water, which removes oxygen from the oxygen-containing gas and also effectively inhibits carbon deposition on the surface of a catalyst and the production of a carbon oxide, which enhances the toleration for fluctuation of the oxygen content in a raw gas.
    Type: Application
    Filed: May 13, 2022
    Publication date: April 10, 2025
    Inventors: Zhe YANG, Jie JIANG, Song WEN, Changsheng ZHANG, Wei XU, Bing SUN, Jinchong ZHAO, Yunfeng ZHU, Shoutao MA, Yuxia ZHANG
  • Publication number: 20250120077
    Abstract: A non-volatile memory device includes at least one memory cell, and the at least one memory cell includes a substrate, a stacked structure, a tunneling dielectric layer, a floating gate, a control gate structure, and an erase gate structure. The stacked structure is disposed on the substrate, and includes a gate dielectric layer, an assist gate, and an insulation layer stacked in order. The tunneling dielectric layer is disposed on the substrate at one side of the stacked structure. The floating gate is disposed on the tunneling dielectric layer and includes an uppermost edge and a curved sidewall. The control gate structure covers the curved sidewall of the floating gate. The erase gate structure covers the floating gate and the control gate structure, and the uppermost edge of the floating gate is embedded in the erase gate structure.
    Type: Application
    Filed: December 18, 2024
    Publication date: April 10, 2025
    Inventors: Der-Tsyr Fan, l-Hsin Huang, Tzung-Wen Cheng, Yu-Ming Cheng, Chen-Ming Tsai, l-Chun Chuang
  • Publication number: 20250113815
    Abstract: Use of insect prevention is provided in some embodiments of the present disclosure, including: providing an insect prevention item, in which a plurality of repeating patterns and a plurality of spacer patterns are represented on a surface of the insect prevention item, each of the plurality of repeating patterns is spaced apart by each of the plurality of spacer pattern, and a viewing angle of one of the plurality of repeating patterns and a spacer pattern neighboring to one of plurality of the repeating patterns represents on a plurality of ommatidias of the flying insect is less than twice of an inter-ommatidial angle of each of the plurality of ommatidias of the flying insect; and disposing the insect prevention item on an outer site of a target item.
    Type: Application
    Filed: April 19, 2024
    Publication date: April 10, 2025
    Inventors: En-Cheng YANG, Hsiang-Wen HSIEH
  • Publication number: 20250114295
    Abstract: The invention relates to composition for skin care. In particular the invention relates to skincare composition comprising a myrrh resin extract, and a processed oat ingredient. The invention also relates to a method of treating the skin using said composition, and to a method for activating lipid production in the skin layers.
    Type: Application
    Filed: October 3, 2024
    Publication date: April 10, 2025
    Inventors: Ramine PARSA, Peter LYTE, Wen-Hwa Ting LI
  • Publication number: 20250120097
    Abstract: A memory device includes a two-dimensional array of access transistors located on a semiconductor substrate; metal interconnect structures embedded in dielectric material layers and electrical connected to electrical nodes of the access transistors; and a two-dimensional array of resistive memory structures embedded in the dielectric material layers. The metal interconnect structures include two first source lines located at a first metal line level and laterally extending along a first horizontal direction; a second source line located at a second metal line level and laterally extending along the first horizontal direction; and a vertical connection structure including a plurality of interconnection via structures and at least one line-level metal structure and providing a vertical electrical connection between the two first source lines and the second source line.
    Type: Application
    Filed: April 8, 2024
    Publication date: April 10, 2025
    Inventors: Sheng-Hung Shih, Kuo-Chi Tu, Wan-Chen Chen, Tzu-Yu Chen, Wen-Ting Chu
  • Publication number: 20250116431
    Abstract: A multi-stage cooling system includes a pressure-resistant container and a parallel-mode cooling device that is at least partially arranged in the pressure-resistant container. The pressure-resistant container can store a dry gas therein that has a dew point temperature being less than ?10° C. and that has a pressure being greater than 1 atm. The parallel-mode cooling device includes two heat exchangers immersed in the dry gas. The two heat exchangers respectively have a first cooling critical value and a second cooling critical value that is less than the first cooling critical value. The parallel-mode cooling device is configured to reduce a temperature of the dry gas to the first cooling critical value through one of the two heat exchangers having a lower operation power, and then further to reduce the temperature of the dry gas through another one of the two heat exchangers having a higher operation power.
    Type: Application
    Filed: August 12, 2024
    Publication date: April 10, 2025
    Inventor: WEN-HSIN LEE
  • Publication number: 20250118912
    Abstract: A bus connection cable reverse-welding structure includes a circuit board, a flat cable, and a first line. The circuit board includes a wiring side, an insertion side, a welding area, a first mating area. A wire exit direction is defined from the wiring side toward the insertion side. The welding area is on the wiring side, and the first mating area is on the insertion side. The flat cable includes a main segment, an attached segment, and a welding end. The main segment extends along the wire exit direction, and the attached segment is attached on the circuit board. The welding end is electrically connected to the welding area. The first line is arranged in the circuit board and includes a first embedded segment and a first extension segment. The first embedded segment is embedded in the circuit board and connected to the welding area.
    Type: Application
    Filed: November 30, 2023
    Publication date: April 10, 2025
    Inventors: Wen-Yu WANG, Chieh-Ming CHENG