Patents by Inventor Wen (Phil) Shih CHEN

Wen (Phil) Shih CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250151559
    Abstract: A display panel and a display device are provided. The display panel includes: a plurality of first pixel units, a plurality of second pixel units, a plurality of third pixel units and a plurality of first data lines. An effective light-emitting area of the first pixel unit is larger than an effective light-emitting area of the second pixel unit, and larger than an effective light-emitting area of the third pixel unit; an orthographic projection of the first data line on the base substrate is not overlapped with an orthographic projection of any one of the first electrode of the first pixel unit, the first electrode of the second pixel unit, and the first electrode of the third pixel unit on the base substrate.
    Type: Application
    Filed: January 13, 2025
    Publication date: May 8, 2025
    Applicants: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Lili DU, Hongjun ZHOU, Wen TAN, Cong LIU
  • Publication number: 20250149380
    Abstract: A method includes adding a first additive to an electroplating solution, wherein the first additive is a relatively weak suppressing agent; adding a second additive to the electroplating solution, wherein the second additive is a relatively strong suppressing agent; adding a third additive to the electroplating solution, wherein the third additive is a leveling agent; and depositing copper using the electroplating solution, wherein most of the copper is nanotwinned grains having a (111)-orientation.
    Type: Application
    Filed: January 18, 2024
    Publication date: May 8, 2025
    Inventors: Ming-Da Cheng, Eugene Chow Chi Hao, Chang-Jung Hsueh, Chun-Fu Wu, Wen-Hsiung Lu
  • Publication number: 20250149812
    Abstract: A card edge connector includes: a housing having a mating slot for insertion of an electronic card; plural terminals retained in the housing; a latch mounted at a first longitudinal end of the housing; a movable key received in the housing; and a rod attached to the housing, wherein the latch and the movable key are connected with opposite ends of the rod, and the movable key is pushable downwards to push the rod to move in a longitudinal direction to bring the latch to a locked state.
    Type: Application
    Filed: October 25, 2024
    Publication date: May 8, 2025
    Inventors: KUO-CHUN HSU, MING-YI GONG, YU-CHE HUANG, XUN WU, PO-FU CHEN, WEN-LUNG HSU
  • Publication number: 20250144710
    Abstract: Provided are system and methods for additive manufacturing, especially using regolith. A system comprises a vacuum chamber configured to contain a material, wherein the material includes a metal fuel and an oxidizer, and an ignition source configured to ignite the material to combustion. The metal fuel includes at least one of magnesium and aluminum. The oxidizer is at least one of lunar regolith, Martian regolith, or a regolith simulant. The systems and methods provide a mechanism for sustainable production of fuels from regolith materials, with limited or not resource requirements from Earth, resulting in more sustainable space exploration.
    Type: Application
    Filed: November 4, 2024
    Publication date: May 8, 2025
    Inventors: Haroon B. Oqab, George B. Dietrich, Boyu Li, Anqi Wang, Jean-Pierre Hickey, John Z. Wen, Connor J. MacRobbie
  • Publication number: 20250147015
    Abstract: A protein analysis platform includes a platform body comprising: a gel working unit provided in a top portion of the platform body and comprising a gel accommodation area for accommodating at least one gel; at least one electrophoresis tank provided along a side of the gel accommodation area and provided with at least one electrode; and a blotting layer stack provided in a bottom portion of the gel working unit and comprising an electrode layer; wherein a removable bottom plate is provided between the gel working unit and the blotting layer stack and detachably corresponds to a bottom side of the gel accommodation area. The protein analysis platform is used for western blotting or next-generation western blotting, wherein the protein analysis platform can quickly complete steps such as gel casting, electrophoresis, and blotting in one platform.
    Type: Application
    Filed: November 8, 2024
    Publication date: May 8, 2025
    Inventors: AN-BANG WANG, WEI-WEN LIU, SI-TSE JIANG, CHIA-WEI HSU, TING-CHI HUANG
  • Publication number: 20250150748
    Abstract: The disclosure discloses a noise reduction headphone, a noise reduction method and apparatus, a storage medium and a processor. The noise reduction headphone includes: a first noise reduction channel, wherein the first noise reduction channel at least includes: at least one first feed-forward microphone, at least one feed-back microphone, a first feed-forward noise reduction processing unit, a feed-back noise reduction processing unit, and a first loudspeaker; and a second noise reduction channel, wherein the second noise reduction channel at least includes: at least one second feed-forward microphone, a second feed-forward noise reduction processing unit, and a second loudspeaker; wherein the first feed-forward noise reduction processing unit and the second feed-forward noise reduction processing unit are configured to process ambient noise signals, the feed-back noise reduction processing unit is configured to process an ear canal noise signal.
    Type: Application
    Filed: December 26, 2022
    Publication date: May 8, 2025
    Inventors: Yu WEN, Hu LI, Jinhua RUAN, Fuhai XIE, Baiyun JIANG
  • Publication number: 20250145940
    Abstract: The present invention provides a transformed strain, comprising: a host cell; a first nucleotide sequence, located inside the host cell, the first nucleotide sequence encoding a PETase, which is derived from Ideonella; and a second nucleotide sequence, located inside the host cell, the second nucleotide sequence comprising a first chaperon nucleotide sequence or a second chaperon nucleotide sequence; wherein the first chaperon nucleotide sequence encodes a molecular chaperon protein (GroELS), and the second chaperon nucleotide sequence encodes a lipase secretion chaperone protein (LsC). The present invention also provides a method for degrading plastic, using said transformed strain for degrading a plastic having PET.
    Type: Application
    Filed: November 6, 2024
    Publication date: May 8, 2025
    Inventors: I-Son NG, Jie-Yao YU, Wan-Wen TING, Chuan-Chieh HSIANG
  • Publication number: 20250147205
    Abstract: An optical lens assembly includes, from an object side to an image side, at least four optical lens elements. At least one of the at least four optical lens elements includes an anti-reflective coating. The at least one optical lens element including the anti-reflective coating is made of a plastic material. The anti-reflective coating is arranged on an object-side surface or an image-side surface of the at least one optical lens element including the anti-reflective coating. The anti-reflective coating includes at least one coating layer. One of the at least one coating layer at the outer of the anti-reflective coating is made of ceramics. The anti-reflective coating includes a plurality of holes, and sizes of the plurality of holes adjacent to the outer of the anti-reflective coating are larger than sizes of the plurality of holes adjacent to the inner of the anti-reflective coating.
    Type: Application
    Filed: January 9, 2025
    Publication date: May 8, 2025
    Inventors: Wen-Yu TSAI, Chien-Pang CHANG, Chi-Wei CHI, Wei-Fong HONG, Chun-Hung TENG, Kuo-Chiang CHU
  • Publication number: 20250147219
    Abstract: A front light module configured to be disposed on a display panel to illuminate the display panel is provided. The front light module includes a light source and a light guide plate. The light guide plate has a first surface facing away from the display panel, a second surface facing the display panel, and a light incident surface facing the light source. The light incident surface connects the first surface and the second surface. The first surface has multiple sets of optical micro-structures. Each of the sets of the optical micro-structures includes multiple optical micro-structures disposed or distributed asymmetrically.
    Type: Application
    Filed: October 9, 2024
    Publication date: May 8, 2025
    Applicant: E Ink Holdings Inc.
    Inventors: Chia Feng Ho, Jen-Yuan Chi, Yu-Nan Pao, Yen-Hao Chen, Yu-Chuan Wen, Hsin-Tao Huang
  • Publication number: 20250151320
    Abstract: A FinFET LDMOS device includes a semiconductor substrate; juxtaposed first well and second well in the semiconductor substrate; semiconductor fins extending on the semiconductor substrate along a first direction, the semiconductor fins including a first fin portion in the first well and a second fin portion in the second well; an extra semiconductor body adjoining the first fin portion and the second fin portion and extending along a second direction; a source region on the first fin portion; a drain region on the second fin portion; a gate covering the semiconductor fin and extending along the second direction, wherein the gate partially overlaps the first fin portion and partially overlaps the second fin portion, and the extra semiconductor body is covered by the gate; and a single-diffusion break structure embedded in the second fin portion and between the gate and drain region.
    Type: Application
    Filed: December 6, 2023
    Publication date: May 8, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi Chuen Eng, Tzu-Feng Chang, Teng-Chuan Hu, Yi-Wen Chen, Yu-Hsiang Lin
  • Publication number: 20250146643
    Abstract: An illumination module includes a light source configured to emit an illumination light beam, a reflective light valve disposed on a path of the illumination light beam and configured to form a plurality of pixels, a lens, and an image sensing module. Each pixel is adapted to be switched between a first state and a second state. The pixels in the first state among the pixels are configured to reflect the illumination light beam into an effective light beam. The pixels in the second state among the pixels are configured to reflect the illumination light beam into a complementary light beam. The lens is disposed on a path of the effective light beam and configured to project the effective light beam to an area to be illuminated. The image sensing module is disposed on a path of a complementary light beam from the reflective light valve and configured to sense the complementary light beam.
    Type: Application
    Filed: November 5, 2024
    Publication date: May 8, 2025
    Applicant: Qisda Corporation
    Inventors: Chao-Shun Yu, Cheng-Chieh Juan, Wen-Chang Chen, Chun-Sheng Hu
  • Publication number: 20250150062
    Abstract: A latch calibration system includes a latch, a clock circuit and a calibration circuit. Latch latches logic data from a data node in an internal node. Latch includes two transistors respectively coupled between data node and internal node. Clock circuit generates first and second clock control signals. Calibration circuit is coupled to clock circuit and latch, and includes two bootstrap circuits coupled to clock circuit respectively. First bootstrap circuit generates a third clock control signal according to first clock control signal, which is output to a gate of first transistor. a high level of third clock control signal is greater than that of first clock control signal. Second bootstrap circuit generates a fourth clock control signal according to the second clock control signal, which is output to a gate of second transistor. A low level of fourth clock control signal is less than that of second clock control signal.
    Type: Application
    Filed: June 18, 2024
    Publication date: May 8, 2025
    Inventors: Hung-Lin WU, Chih-Wen YANG, Yu-Chen LO
  • Publication number: 20250149828
    Abstract: A card edge connector includes: a connector body having a card slot and plural terminals arranged on opposite sides of the card slot; a latch mounted at an end of connector body; and a releasing member including a pair of levers disposed at opposite sides of the connector body and a mover, wherein first ends of the levers are connected with the latch, second ends are connected with the mover, and when the card is inserted into the card slot the mover is pushed to move downwards companied with a downward movement of the second ends and an upward movement of the first ends of the levers, the upward movement of the first ends drive the latch to lock with the card and when the card is pulled out the mover is released from a pressure of the card and reset to unlock the latch from the electronic card.
    Type: Application
    Filed: October 30, 2024
    Publication date: May 8, 2025
    Inventors: KUO-CHUN HSU, MING-YI GONG, WEN-LUNG HSU, XUN WU, PO-FU CHEN
  • Publication number: 20250150571
    Abstract: The invention relates to a display device which comprises a light source, a grid structure and a photo interrupter. The grid structure is disposed above the light source and can move left and right relative to the light source. When the grid structure does not block the photo interrupter, the light source receives a first signal, and when the grid structure blocks the photo interrupter, the light source receives a second signal.
    Type: Application
    Filed: June 3, 2024
    Publication date: May 8, 2025
    Inventors: Ching-Tien Lien, Kai-Wen CHEN, Chi-Tseng CHANG, Kuo-Shu HUANG
  • Publication number: 20250149324
    Abstract: A method for forming a semiconductor device structure includes forming a fin structure over a substrate. The fin structure has a base layer, and the fin structure has multiple sacrificial layers and multiple semiconductor layers laid out in an alternating manner over the base layer. The method also includes partially removing the fin structure to form an opening exposing side surfaces of the semiconductor layers, the sacrificial layers, and the base layer. The method further includes partially or completely removing the base layer to form a recess, forming a protective structure in the recess, and forming an epitaxial structure filling the opening. In addition, the method includes partially removing the substrate from a backside surface of the substrate to form a contact opening exposing the protective structure and extending towards the epitaxial structure. The method includes forming a backside conductive contact in the contact opening.
    Type: Application
    Filed: November 8, 2023
    Publication date: May 8, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hsun LIN, Wen-Chiang HONG, Jiun-Jie CHAO, Jyh-Huei CHEN
  • Publication number: 20250150476
    Abstract: Systems and methods for entity classification via an artificial intelligence model using a defined taxonomy framework are described. Entity classification includes generating a first query for a classification model, the first query including a first set of options for classification of an entity at a first classification granularity level of a taxonomy framework, providing the first query comprising the first set of options for classification to the classification model, receiving, from the classification model, a selection of one or more options of the first set of options for classification, and determining a classification of the entity based at least in part on the selection of the one or more options of the first set of options.
    Type: Application
    Filed: August 26, 2024
    Publication date: May 8, 2025
    Inventors: Yi Shen, Cedrik Ho, Mei Zhou, Rajiv Murthy, Shan-Wen Yan
  • Publication number: 20250151366
    Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a core region and an input/output (I/O) region and then forming a first metal gate on the core region and a second metal gate on the I/O region. Preferably, the first metal gate includes a first gate dielectric layer, the second metal gate includes a second gate dielectric layer, the first gate dielectric layer and the second gate dielectric layer having different shapes such that the first gate dielectric layer includes an I-shape and the second gate dielectric layer includes a U-shape.
    Type: Application
    Filed: December 6, 2023
    Publication date: May 8, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Zi-Ting Huang, Ching-Ling Lin, Wen-An Liang
  • Publication number: 20250149463
    Abstract: Methods, systems, and devices for top die back-side marking for memory systems are described. One or more alignment marks may be added to the back-side of a top memory die in a multi-layer memory device and used to align a position of the top memory die relative to a position of a memory die below the top memory die. The alignment marks may be formed on the top memory die during the manufacturing process of the multi-layer memory device. Operations for forming the alignment marks are described using various semiconductor fabrication techniques. Operations are also disclosed for using the alignment marks to modify placement of the top memory die to reduce the alignment offset in the manufacturing process of subsequent memory dies.
    Type: Application
    Filed: October 28, 2024
    Publication date: May 8, 2025
    Inventors: Po Chien Li, Yu Kai Kuo, Yi Wen Chen, Ming Wei Tsai, Chien Nan Fan, Chun Ming Huang, Angelo Oria Espina, Chun Jen Chang
  • Publication number: 20250149996
    Abstract: A three-level power factor rectifier includes a diode bridge arm, a bridge arm assembly, an input inductor, a capacitor bank, and a controller. The first bridge arm includes a first switch, a second switch, a third switch, and a fourth switch connected in series and in sequence. When the controller determines that a loading is less than a load threshold, the controller controls the three-level power factor rectifier entering a burst mode. In the burst sleep period, when a voltage value of an AC power source is greater than a first threshold, the first switch and the second switch are turned off; when the voltage value is less than a second threshold, the third switch and the fourth switch are turned on. When entering the burst period from the burst sleep period, the controller turns on the second switch and the third switch for a specific time period.
    Type: Application
    Filed: March 21, 2024
    Publication date: May 8, 2025
    Inventors: Yi-Li SU, Chien-Hung LIU, Wen-Lung HUANG, Chang-Hung LIAO, Po-Yi YEH
  • Publication number: 20250149593
    Abstract: The present application discloses a lithium-supplementing additive, and a preparation method therefor and an application thereof. The lithium-supplementing additive comprises a particulate lithium-supplementing material and also comprises lithium fluoride; moreover, the lithium fluoride is at least bonded to the surface of the lithium-supplementing material, and the lithium fluoride is generated by the reaction between an organic fluorine source and residual alkali contained in the lithium-supplementing material.
    Type: Application
    Filed: January 17, 2023
    Publication date: May 8, 2025
    Applicant: SHENZHEN INNOVAZONE TECHNOLOGY CO., LTD.
    Inventors: Chengben ZHU, Yuanxin WAN, Lingyong KONG, Zeqin ZHONG, Wen ZHONG