Abstract: A non-volatile random access memory (NV-RAM) and an operation method thereof are provided. The NV-RAM includes a latch unit, a switch, and a first to fourth non-volatile memory elements. First terminals of the first and the third non-volatile memory elements respectively couple to a first voltage and a second voltage. A second terminal of the first non-volatile memory element and a first terminal of the second non-volatile memory element are coupled to a first terminal of the latch unit. A second terminal of the third non-volatile memory element and a first terminal of the fourth non-volatile memory element are coupled to a second terminal of the latch unit. Second terminals of the second and the fourth non-volatile memory element are coupled to a first terminal of the switch. A second terminal of the switch is coupled to a third voltage.

Abstract: A process variation detection apparatus and a process variation detection method are provided. The process variation detection apparatus includes a process variation detector and a compensation signal generator. The process variation detector includes a first process variation detection component, a second process variation detection component and a current comparator. The channel of the first process variation detection component is a first conductive type, and the channel of the second process variation detection component is a second conductive type, wherein the above-mentioned first conductive type is different from the second conductive type. The current comparator is connected to the first process variation detection component and the second process variation detection component for comparing the current difference between the two components and outputting a current comparison result.

Abstract: A jet propulsion construction toy assembly includes a container mounted on a movable brick assembly. A launching unit includes a launching seat permitting extension of a nozzle of the container thereinto and having an inlet. When the nozzle extends into the launching seat, an actuator mounted movably in said launching seat is operable to engage the nozzle such that said container is filled with fluid including air and liquid and pumped out of a barrel by a pump through first and second conduits, the inlet and the nozzle. Thereafter, when the nozzle is released from the launching seat due to disengagement between the nozzle and the actuator, jet of the fluid from the container through the nozzle forms a propulsion force to drive movement of a combination of the brick assembly and the container away from the launching unit.

Abstract: A resistive random access memory (RRAM) and a verifying method thereof are provided. The RRAM comprises at least one resistive memory cell. The resistive memory cell comprises a resistive memory element and a transistor, wherein one terminal of the resistive memory element is coupled to a first terminal of the transistor. The verifying method comprises the following steps: Whether the resistive memory cell passes verification is determined. During a first time period and under the circumstance that the resistive memory cell fails to pass verification, a reference voltage is applied to the other terminal of the resistive memory element and a voltage pulse is applied to a second terminal of the transistor according to a voltage signal to write a reverse voltage to the resistive memory cell.

Abstract: A phase change memory with an operating current that can be gradually increased or gradually decreased. The phase change memory has a phase change storage element, a transistor, and a control circuit. The transistor is operable to adjust the operating current flowing through the phase change storage element. The transistor has a first terminal coupled to a voltage source, a second terminal coupled to the phase change storage element, and a control terminal receiving a control signal from the control circuit. The control circuit is specially designed to limit the transistor in a linear region.

Abstract: A data programming circuit for storing a writing data into a memory cell is provided. The data programming circuit includes a control circuit and a current generating circuit. The control circuit generates a control signal according to the writing data. The current generating circuit provides a writing current to the memory cell to change a crystalline state of the memory cell. The writing current has a pulse width corresponding to the writing data, and the crystalline state corresponds to the writing data.

Abstract: A phase change memory with an operating current that can be gradually increased or gradually decreased. The phase change memory has a phase change storage element, a transistor, and a control circuit. The transistor is operable to adjust the operating current flowing through the phase change storage element. The transistor has a first terminal coupled to a voltage source, a second terminal coupled to the phase change storage element, and a control terminal receiving a control signal from the control circuit. The control circuit is specially designed to limit the transistor in a linear region.

Abstract: A resistive random access memory (RRAM) and a verifying method thereof are provided. The RRAM comprises at least one resistive memory cell. The resistive memory cell comprises a resistive memory element and a transistor, wherein one terminal of the resistive memory element is coupled to a first terminal of the transistor. The verifying method comprises the following steps: Whether the resistive memory cell passes verification is determined. During a first time period and under the circumstance that the resistive memory cell fails to pass verification, a reference voltage is applied to the other terminal of the resistive memory element and a voltage pulse is applied to a second terminal of the transistor according to a voltage signal to write a reverse voltage to the resistive memory cell.

Abstract: A test structure including at least one ground pad, an input pad, at least one first through-silicon via (TSV), at least one second TSV and an output pad is disclosed. The ground pad receives a ground signal during a test mode. The input pad receives a test signal during the test mode. The first TSV is coupled to the input pad. The output pad is coupled to the second TSV. No connection line occurs between the first and the second TSVs. During the test mode, a test result is obtained according to the signal of at least one of the first and the second TSVs, and structural characteristics can be obtained according to the test result.

Abstract: The power brick assembly includes a solar energy collecting plate carried on a carrier for collecting solar energy to generate electrical energy. A first connecting port is mounted on the carrier so that the carrier is movable relative to the first connecting port. A mechanical rotary power generating unit includes a second connecting port mounted on a brick-like casing and connected electrically and detachably to the first connecting port so that the first connecting port is movable relative to the second connecting port. The brick-like casing receives a battery module for supplying electric power, a driving module for generating a mechanical rotary power output in response to an electric power input, and a control module operable to output the electric power input based on one of the electrical energy from the solar energy collecting plate and the electric power from the battery module.

Abstract: A data programming circuit for storing a writing data into a memory cell is provided. The data programming circuit includes a control circuit and a current generating circuit. The control circuit generates a control signal according to the writing data. The current generating circuit provides a writing current to the memory cell to change a crystalline state of the memory cell. The writing current has a pulse width corresponding to the writing data, and the crystalline state corresponds to the writing data.

Abstract: A process variation detection apparatus and a process variation detection method are provided. The process variation detection apparatus includes a process variation detector and a compensation signal generator. The process variation detector includes a first process variation detection component, a second process variation detection component and a current comparator. The channel of the first process variation detection component is a first conductive type, and the channel of the second process variation detection component is a second conductive type, wherein the above-mentioned first conductive type is different from the second conductive type. The current comparator is connected to the first process variation detection component and the second process variation detection component for comparing the current difference between the two components and outputting a current comparison result.

Abstract: A voltage compensation circuit, a multi-level memory device with the same, and a voltage compensation method for reading the multi-level memory device are provided. When a memory cell is read, a reference voltage applied to the memory device is adjusted according to variation of characteristics of a drift resistance of a reference cell. The increased value of the reference voltage (i.e. a voltage difference) corresponds to a resistance variation caused by a drift condition. The drift compensation mechanism is adaptive to a compensation circuit of a read driver of the memory device, which can compensate variation of the voltage level when data is read from the memory cell. When the resistance drift occurs, a drift amount is calculated and is added to the reference voltage, in order to avoid the error in judgement caused by the resistance drift when the stored data is read out.

Abstract: A data programming circuit for storing a writing data into a memory cell is provided. The data programming circuit includes a control circuit and a current generating circuit. The control circuit generates a control signal according to the writing data. The current generating circuit provides a writing current to the memory cell to change a crystalline state of the memory cell. The writing current has a pulse width corresponding to the writing data, and the crystalline state corresponds to the writing data.

Abstract: A phase change memory (PCM) in which the phase change storage element is crystallized by a gradually increasing/decreasing operating current. The PCM comprises a switching circuit, the phase change storage element, a bit select switch, a pulse generating module, and a counting module. The switching circuit comprises a plurality of switches, selectively providing branch paths to an output terminal of a current source. The bit select switch controls the conduction between the phase change storage element and the output terminal of the current source. The pulse generating module outputs a pulse signal oscillating between high and low voltage levels. When enabled, the counting module counts the oscillations of the pulse signal, and outputs the count result by a set of digital data. The set of digital data are coupled to the switching circuit to control the switches therein.

Abstract: A verification circuit for a phase change memory array is provided. A sensing unit senses a sensing voltage from a memory cell of the phase change memory array according to an enable signal. A comparator generates a comparing signal according to the sensing voltage and a reference voltage, so as to indicate whether the memory cell is in a reset state. A control unit generates a control signal according to the enable signal. An operating unit generates a first signal according to the control signal, so as to indicate whether the comparator is active. An adjustment unit provides a writing current to the cell, and increases the writing current according to the control signal until the comparing signal indicates that the memory cell is in a reset state.

Abstract: A method and an apparatus is provided for monitoring and adjusting a power level of a transmitting component. The method comprises receiving a request from a remote unit to provide a power level associated with a transmitting component, wherein the request is transmitted over a communications protocol. The method includes measuring a power level of a signal provided by the transmitting component in response to receiving the request from the remote unit, and providing the measured power level to the remote unit over the communications protocol.

Abstract: A voltage compensation circuit, a multi-level memory device with the same, and a voltage compensation method for reading the multi-level memory device are provided. When a memory cell is read, a reference voltage applied to the memory device is adjusted according to variation of characteristics of a drift resistance of a reference cell. The increased value of the reference voltage (i.e. a voltage difference) corresponds to a resistance variation caused by a drift condition. The drift compensation mechanism is adaptive to a compensation circuit of a read driver of the memory device, which can compensate variation of the voltage level when data is read from the memory cell. When the resistance drift occurs, a drift amount is calculated and is added to the reference voltage, in order to avoid the error in judgement caused by the resistance drift when the stored data is read out.

Abstract: A metal-air fuel cell module includes a cap seat connected detachably to a casing and having a plug portion extending into an inner accommodating space in the casing for plugging an opening in the casing; a conductive gas-diffusion sheet disposed in the casing for covering sealingly air inlets in the casing, and permitting air to pass through; an electrolyte solution filled in the inner accommodating space; a metal sheet disposed in the inner accommodating space and connected detachably to the plug portion of the cap seat; a first electrode plate mounted on the casing, extending into the inner accommodating space and in electrical contact with the gas-diffusion sheet; and a second electrode plate mounted in the cap seat, extending into the inner accommodating space and in electrical contact with the metal sheet.

Abstract: A memory having a memory cell, a resistance estimator and a write current generator. The resistance estimator is coupled to the memory cell to estimate the resistance of the memory cell and outputs an estimated resistance level. According to the estimated resistance level, the write current generator generates a write current to flow through the memory cell and to change the resistance of the memory cell. The write current is in a pulse form, and the write current generator sets the pulse width, or magnitude, or both the pulse width and the magnitude of the write current according to the estimated resistance level.