Patents by Inventor Wen-Shen Chou

Wen-Shen Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230023317
    Abstract: Systems and methods are provided for designing an integrated circuit device. In one example, a method for designing an integrated circuit device may include the operations of: receiving a schematic diagram of the integrated circuit device; generating, by a simulation program, a first transient simulation of the integrated circuit device based on the schematic diagram; determining from the first transient simulation of the integrated circuit device a plurality of maximum voltage change values between conductor networks (nets) within the schematic diagram of the integrated circuit device; storing the plurality of maximum voltage change values for the schematic diagram of the integrated circuit device in a computer readable medium; and utilizing, by a layout program, the stored plurality of maximum voltage change values to generate a layout design for the integrated circuit device according to one or more high voltage design constraints.
    Type: Application
    Filed: March 8, 2022
    Publication date: January 26, 2023
    Inventors: Shenggao Li, Szu-Chun Tsao, Wen-Shen Chou
  • Publication number: 20220358273
    Abstract: Various techniques are disclosed for automatically generating sub-cells for a non-final layout of an analog integrated circuit. Device specifications and partition information for the analog integrated circuit is received. Based on the device specifications and the partition information, first cut locations for a first set of cuts to be made along a first direction of a non-final layout of the analog integrated circuit and second cut locations for a second set of cuts to be made along a second direction in the non-final layout are determined. The first set of cuts are made in the non-final layout at the cut locations to produce a temporary layout. The second set of cuts are made in the temporary layout at the cut locations to produce a plurality of sub-cells.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chiang Chang, Wen-Shen Chou, Yung-Chow Peng, Yung-Hsu Chuang, Yu-Tao Yang, Bindu Madhavi Kasina
  • Publication number: 20220352887
    Abstract: A semiconductor device includes a hysteresis block configured to generate an output voltage at corresponding disabling enabling voltage levels and a core-voltage-gated (CVG) device configured to receive a core voltage, an input terminal of the hysteresis block is coupled to a control node. The CVG device is configured to alter a control voltage at the control node so as to cause the output voltage of the hysteresis block to be generated at the disabling voltage level in response to the core voltage being at or below a first trigger level. Additionally, the CVG device is configured to alter the control voltage at the control node so as to cause the output voltage of the hysteresis block to be generated at the enabling voltage level in response to the core voltage being at or above a second trigger level, the second trigger level being above the first trigger level.
    Type: Application
    Filed: July 30, 2021
    Publication date: November 3, 2022
    Inventors: Po-Zeng KANG, Wen-Shen CHOU, Yung-Chow PENG
  • Publication number: 20220309221
    Abstract: Techniques for generating one or more non-final layouts for an analog integrated circuit are disclosed. The techniques include generating a non-final layout of an analog integrated circuit based on device specifications, partitioning the non-final layout into a plurality of sub-cells, merging the verified sub-cells to form a merged layout of the analog integrated circuit, and performing quality control checks on the merged layout. Additionally or alternatively, generating the non-final layout can include determining an allowable spacing between adjacent cells of different cell types or inserting one or more filler cells into a filler zone in the non-final layout.
    Type: Application
    Filed: March 25, 2021
    Publication date: September 29, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Tao Yang, Wen-Shen Chou, Yung-Chow Peng, Yung-Hsu Chuang
  • Patent number: 11429775
    Abstract: Various techniques are disclosed for automatically generating sub-cells for a non-final layout of an analog integrated circuit. Device specifications and partition information for the analog integrated circuit is received. Based on the device specifications and the partition information, first cut locations for a first set of cuts to be made along a first direction of a non-final layout of the analog integrated circuit and second cut locations for a second set of cuts to be made along a second direction in the non-final layout are determined. The first set of cuts are made in the non-final layout at the cut locations to produce a temporary layout. The second set of cuts are made in the temporary layout at the cut locations to produce a plurality of sub-cells.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: August 30, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chiang Chang, Wen-Shen Chou, Yung-Chow Peng, Yung-Hsu Chuang, Yu-Tao Yang, Bindu Madhavi Kasina
  • Publication number: 20220246602
    Abstract: A method of generating a layout design of an integrated circuit includes forming an active zone and partitioning the active zone into a center portion between a first side portion and a second side portion. The method also includes forming a plurality of gate-strips and forming a routing line. The plurality of gate-strips includes a first group of gate-strips intersecting the active zone over first channel regions in the center portion, a second group of gate-strips intersecting the active zone over second channel regions in the center portion, a third group of gate-strips intersecting the active zone over third channel regions in the first side portion, and a fourth group of gate-strips intersecting the active zone over fourth channel regions in the second side portion.
    Type: Application
    Filed: April 18, 2022
    Publication date: August 4, 2022
    Inventors: Yu-Tao YANG, Wen-Shen CHOU, Yung-Chow PENG
  • Publication number: 20220122913
    Abstract: A semiconductor device includes transistors and a resistor. The transistors are connected in series between a power terminal and a ground terminal, and gate terminals of the transistors being connected together. The resistor is overlaid above the transistors. The resistor is connected between a source terminal of the transistors and the ground terminal.
    Type: Application
    Filed: January 3, 2022
    Publication date: April 21, 2022
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Zeng KANG, Wen-Shen CHOU, Yung-Chow PENG
  • Patent number: 11309306
    Abstract: An integrated circuit includes an active zone having a center portion adjoining a first side portion and a second side portion. A first transistor having a gate formed over one of the first channel regions in the center portion has a first threshold-voltage. A second transistor having a gate formed over one of the second channel regions in the center portion has a second threshold-voltage. A third transistor having a gate formed over one of the third channel regions in the first side portion has a third threshold-voltage. A fourth transistor having a gate formed over one of the fourth channel regions in the second side portion has a fourth threshold-voltage. A first average of the first threshold-voltage and the second threshold-voltage is larger than a second average of the third threshold-voltage and the fourth threshold-voltage by a predetermined threshold-voltage offset.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: April 19, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Tao Yang, Wen-Shen Chou, Yung-Chow Peng
  • Publication number: 20220082451
    Abstract: A semiconductor device includes a plurality of active area structures. One or more active devices include portions of the plurality of active area structures. A metal layer is formed on the plurality of active area structures and separated from the one or more active devices by one or more dummy gate layers. The metal layer is configured to measure, due to a change of resistance in the metal layer, a temperature of the plurality of active area structures.
    Type: Application
    Filed: November 23, 2021
    Publication date: March 17, 2022
    Inventors: Po-Zeng KANG, Wen-Shen CHOU, Yung-Chow PENG
  • Patent number: 11270057
    Abstract: A method includes: generating a design layout according to a circuit design by placing first and second components; identifying a first area and a second area between the first component and the second component; and determining a first cell configuration of the first component according to the first component and a second cell configuration of the second component according to the second component. The method further includes selecting a first cell comprising a first capacitor from a cell library, wherein the first cell has a third cell configuration identical to the first cell configuration; selecting a second cell comprising a second capacitor from the cell library, wherein the second cell has a fourth cell configuration identical to the second cell configuration; placing a first cell array formed of the first cell in the first area; and placing a second cell array formed of the second cell in the second area.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: March 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Tao Yang, Yung-Hsu Chuang, Wen-Shen Chou, Yung-Chow Peng
  • Publication number: 20220050950
    Abstract: A method includes: generating a design layout according to a circuit design by placing first and second components; identifying a first area and a second area between the first component and the second component; and determining a first cell configuration of the first component according to the first component and a second cell configuration of the second component according to the second component. The method further includes selecting a first cell comprising a first capacitor from a cell library, wherein the first cell has a third cell configuration identical to the first cell configuration: selecting a second cell comprising a second capacitor from the cell library, wherein the second cell has a fourth cell configuration identical to the second cell configuration; placing a first cell array formed of the first cell in the first area; and placing a second cell array formed of the second cell in the second area.
    Type: Application
    Filed: August 12, 2020
    Publication date: February 17, 2022
    Inventors: YU-TAO YANG, YUNG-HSU CHUANG, WEN-SHEN CHOU, YUNG-CHOW PENG
  • Publication number: 20220037312
    Abstract: An IC device includes a transistor including a gate structure between first and second active areas, a first S/D metal portion overlying the first active area, and a second S/D metal portion overlying the second active area. A load resistor including a third S/D metal portion is positioned on a dielectric layer and in a same layer as the first and second S/D metal portions. A first via overlies the first S/D metal portion, second and third vias overlie the third S/D metal portion, and a first conductive structure is configured to electrically connect the first via to the second via.
    Type: Application
    Filed: July 29, 2020
    Publication date: February 3, 2022
    Inventors: Po-Zeng KANG, Wen-Shen CHOU, Yung-Chow PENG
  • Patent number: 11238207
    Abstract: A method for fabricating an integrated circuit is provided. The method includes: receiving a cell schematic of a unit cell of the integrated circuit; when an intrinsic gain of a transistor of the unit cell falls outside a predetermined range of gain values, revising a set of parameter values for a set of size parameters of the unit cell in the cell schematic, wherein the intrinsic gain of the transistor of the unit cell characterized by the revised set of parameter values falls within the predetermined range of gain values; generating a cell layout of the unit cell according to the cell schematic indicating the revised set of parameter values for the set of size parameters; and fabricating the integrated circuit according to the cell layout of the unit cell.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: February 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yung-Hsu Chuang, Wen-Shen Chou, Jie-Ren Huang, Yu-Tao Yang, Yung-Chow Peng, Yun-Ru Chen
  • Patent number: 11217526
    Abstract: A semiconductor device includes transistors and a resistor. The transistors are connected in series between a power terminal and a ground terminal, and gate terminals of the transistors being connected together. The resistor is overlaid above the transistors. The resistor is connected between a source terminal of the transistors and the ground terminal.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: January 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Zeng Kang, Wen-Shen Chou, Yung-Chow Peng
  • Patent number: 11215513
    Abstract: A semiconductor device includes a plurality of active area structures. One or more active devices include portions of the plurality of active area structures. A metal layer is formed on the plurality of active area structures and separated from the one or more active devices by one or more dummy gate layers. The metal layer is configured to measure, due to a change of resistance in the metal layer, a temperature of the plurality of active area structures.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: January 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Zeng Kang, Wen-Shen Chou, Yung-Chow Peng
  • Publication number: 20210390245
    Abstract: A semiconductor device including a first active region having a first active configuration, a second active region having a second, and different, active configuration, and a transition cell arranged between the first and second active regions in which the transition cell has a transitional configuration that is different from and compatible with both the first active configuration and the second active configuration.
    Type: Application
    Filed: August 30, 2021
    Publication date: December 16, 2021
    Inventors: Yung-Hsu CHUANG, Wen-Shen CHOU, Yung-Chow PENG, Yu-Tao YANG, Yun-Ru CHEN
  • Publication number: 20210350063
    Abstract: Systems, methods, and devices are disclosed herein for developing a cell design. Operations of a plurality of electrical cells are simulated to collect a plurality of electrical parameters. A machine learning model is trained using the plurality of electrical parameters. The trained machine learning model receives data having cell layout design constraints. The trained machine learning model determines a cell layout for the received data based on the plurality of electrical parameters. The cell layout is provided for further characterization of electrical performance within the cell layout design constraints.
    Type: Application
    Filed: July 26, 2021
    Publication date: November 11, 2021
    Inventors: Wen-Shen Chou, Jie-Ren Huang, Yu-Tao Yang, Yung-Chow Peng, Yung-Hsu Chuang
  • Patent number: 11106855
    Abstract: Systems, methods, and devices are disclosed herein for developing a cell design. Operations of a plurality of electrical cells are simulated to collect a plurality of electrical parameters. A machine learning model is trained using the plurality of electrical parameters. The trained machine learning model receives data having cell layout design constraints. The trained machine learning model determines a cell layout for the received data based on the plurality of electrical parameters. The cell layout is provided for further characterization of electrical performance within the cell layout design constraints.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wen-Shen Chou, Jie-Ren Huang, Yu-Tao Yang, Yung-Chow Peng, Yung-Hsu Chuang
  • Patent number: 11106854
    Abstract: A method including the operations of receiving a preliminary device layout including a plurality of active areas, analyzing the preliminary device layout to identify empty areas between the plurality of active areas, determining the configurations of the active areas bordering the empty areas, selecting a transition cell from a transition cell library in which the transition cell has a transitional configuration for reducing density gradient effects in the active areas adjacent the transition cell, and inserting the transition cells into the empty areas to define a modified device layout.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: August 31, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Hsu Chuang, Wen-Shen Chou, Yung-Chow Peng, Yu-Tao Yang, Yun-Ru Chen
  • Publication number: 20210256194
    Abstract: A device includes a first cell active area asymmetrically positioned in a first device column between a first barrier line and a second barrier line, a second cell active area asymmetrically positioned in a second device column between the first barrier line and a third barrier line, where the first cell has a first cell length in a first direction perpendicular to the first barrier line which is three times a second cell length in the first direction. The first cell active area and the second cell active area are a first distance from the first barrier line, and the first cell active area is a second distance from the second barrier line, and the second cell active area is the second distance away from the third barrier line.
    Type: Application
    Filed: May 4, 2021
    Publication date: August 19, 2021
    Inventors: Yu-Tao YANG, Wen-Shen CHOU, Yung-Chow PENG