Abstract: This disclosure relates to a method of making a semiconductor device. The method includes comparing a schematic design of the semiconductor device to a layout design of the semiconductor device. The method further includes generating layout style information based on the layout design and generating array edge information based on the layout design and the schematic design. The method further includes selectively revising the layout design using smart dummy insertion using the layout style information and the array edge information. The method further includes performing a design rule check on the revised layout design using the layout style information and the array edge information. This disclosure also relates to a system for making a semiconductor device and a semiconductor device.

Abstract: One or more embodiments of techniques or systems for variation factor assignment for a device are provided herein. In some embodiments, a peripheral environment is determined for a device. A peripheral environment is a layout structure or an instance. When the peripheral environment is the layout structure, a variation factor is assigned to the device based on an architecture associated with the layout structure. When the peripheral environment is the instance, the variation factor is assigned to the device based on a bounding window created for the instance. In this manner, variation factor assignment is provided, such that a first device within a first block of a die has a different variation factor than a second device within a second block of the die, thus giving finer granularity to variation factor assignments.

Abstract: A device includes a first and a second MOS device cascaded with the first MOS device to form a first finger. A drain of the first MOS device and a source of the second MOS device are joined to form a first common source/drain region. The device further includes a third and a fourth MOS device cascaded with the third MOS device to form a second finger. A drain of the third MOS device and a source of the fourth MOS device are joined to form a second common source/drain region. The first and the second common source/drain regions are electrically disconnected from each other. Sources of the first and the third MOS devices are interconnected. Drains of the second and the fourth MOS devices are interconnected. Gates of the first and the third MOS devices are interconnected. Gates of the second and the fourth MOS devices are interconnected.

Abstract: A multi-step density gradient smoothing layout style is disclosed in which a plurality of unit cells are arranged into an array with a feature density. One or more edges of the array is bordered by a first edge sub-array which has a feature density that is less than the feature density of the array. The first edge sub-array is bordered by second edge sub-array which has a feature density that is less than the feature density of the first edge sub-array, and is approaching that of the background circuitry.

Abstract: Among other things, an arrangement for a digital-to-analog converter (DAC) is provided herein. In some embodiments, a metal-oxide semiconductor (MOS) array of the DAS comprises one or more cells respectively comprising one or more current sources. The current sources comprise one or more transistors having a horizontal gate layout. A switch arrangement of the DAS, to which the MOS array is connected, comprises one or more transistors having a vertical gate layout. Accordingly, in some embodiments, a DAC is provided which comprises transistors having a vertical gate layout and transistors having a horizontal gate layout.

Abstract: Among other things, one or more techniques for graded dummy insertion and a resulting array are provided herein. For example an array is a metal oxide semiconductor (MOS) array, a metal oxide metal (MOM) array, or a resistor array. In some embodiments, a first region and a second region are identified based on a density gradient between a first pattern density associated with the first region and a second pattern density associated with the second region. For example, the first pattern density and the second pattern density are gate densities and/or poly densities. To this end, a dummy region is inserted between the first region and the second region, the dummy region includes a graded pattern density based on a first adjacent pattern density and a second adjacent pattern density. In this manner, graded dummy insertion is provided, thus enhancing edge cell performance for an array, for example.

Abstract: The present disclosure relates to a method of optimizing the area of series gate layout structures for FinFET devices. The method analyzes an integrated chip (IC) layout to determine a first gate material density along a first direction and to separately determine a second gate material density along a second direction based upon the first gate material density. A number of series gate stages for a FinFET (field effect transistor) device having a gate length along the second direction, is chosen based upon the second gate material density and one or more device performance parameters of the FinFET device. By analyzing the density of gate material in separate directions, the effective length of the gate of the FinFET can be increased without increasing the size of the transistor array.

Abstract: A device includes a first and a second MOS device cascaded with the first MOS device to form a first finger. A drain of the first MOS device and a source of the second MOS device are joined to form a first common source/drain region. The device further includes a third and a fourth MOS device cascaded with the third MOS device to form a second finger. A drain of the third MOS device and a source of the fourth MOS device are joined to form a second common source/drain region. The first and the second common source/drain regions are electrically disconnected from each other. Sources of the first and the third MOS devices are interconnected. Drains of the second and the fourth MOS devices are interconnected. Gates of the first and the third MOS devices are interconnected. Gates of the second and the fourth MOS devices are interconnected.

Abstract: The present disclosure provides a system and method of designing an integrated circuit. A plurality of devices are selected and properties assigned to each of the plurality of devices. These plural devices having assigned properties are then combined into a macro cell whereby a density gradient pattern is generated for the macro cell. Layout dependent effect (LDE) parameters are determined for the macro cell as a function of the combination of plural devices, and electrical performance characteristics for the macro cell are simulated. A layout distribution of the plurality of devices within the macro cell can then be determined as a function of one or more of the simulated electrical performance characteristics, determined LDE parameters, and generated density gradient pattern. A design layout of an integrated circuit can be generated corresponding to the layout distribution for the macro cell.

Abstract: This disclosure relates to a method of making a semiconductor device. The method includes comparing a schematic design of the semiconductor device to a layout design of the semiconductor device. The method further includes generating layout style information based on the layout design and generating array edge information based on the layout design and the schematic design. The method further includes selectively revising the layout design using smart dummy insertion using the layout style information and the array edge information. The method further includes performing a design rule check on the revised layout design using the layout style information and the array edge information. This disclosure also relates to a system for making a semiconductor device and a semiconductor device.

Abstract: Among other things, one or more techniques for graded dummy insertion and a resulting array are provided herein. For example an array is a metal oxide semiconductor (MOS) array, a metal oxide metal (MOM) array, or a resistor array. In some embodiments, a first region and a second region are identified based on a density gradient between a first pattern density associated with the first region and a second pattern density associated with the second region. For example, the first pattern density and the second pattern density are gate densities and/or poly densities. To this end, a dummy region is inserted between the first region and the second region, the dummy region includes a graded pattern density based on a first adjacent pattern density and a second adjacent pattern density. In this manner, graded dummy insertion is provided, thus enhancing edge cell performance for an array, for example.

Abstract: An amplifier drives the gate of a master source follower and of at least one slave source follower to form a low-dropout (LDO) regulator. Alternatively, a charge pump drives the master source follower to form the regulator. Additional slave source followers may be used in conjunction with the charge pump and the master source follower to improve the regulator performance.

Abstract: A system and method for converting a digital signal to an analog signal is provided. The present disclosure provides a digital-to-analog converter (DAC) that can convert a large bit value digital signal to a corresponding analog signal. In accordance with an embodiment, a method comprises receiving portions of a digital signal by a plurality of sub-DACs; converting the portions of the digital signal to a corresponding analog signal by the plurality of sub-DACs; biasing one or more of the plurality of sub-DACs; and calibrating the portions of a digital signal by one or more calibration elements.

Abstract: A method includes generating a first current, wherein the first current flows through a first resistor and a first bipolar transistor. A first end of the first resistor is serially connected to an emitter-collector path of the first bipolar transistor, and a second end of the resistor is connected to an input of an operational amplifier. A second current is generated to flow through a second resistor that is connected to the input of the operational amplifier. An emitter of a second bipolar transistor is connected to a base of the first bipolar transistor, wherein a base and a collector of the second bipolar transistor are connected to VSS. The first and the second currents are added to generate a third current, which is mirrored to generate a fourth current proportional to the third current. The fourth current is conducted through a third resistor to generate an output reference voltage.

Abstract: A multi-step density gradient smoothing layout style is disclosed in which a plurality of unit cells are arranged into an array with a feature density. One or more edges of the array is bordered by a first edge sub-array which has a feature density that is less than the feature density of the array. The first edge sub-array is bordered by second edge sub-array which has a feature density that is less than the feature density of the first edge sub-array, and is approaching that of the background circuitry.

Abstract: A driver utilizes selective biasing of the terminal of an operational amplifier to reduce offset in the operational amplifier output. Each operational amplifier input includes a differential input pair of transistors including a NMOS transistor and PMOS transistor. At low and high ends of the input voltage range these transistors are selectively and individually coupled to either a standard input or biased to be on so as to contribute offset for offset compensation. The transistors are biased in a conventional manner for input voltages between the low and high ends of the voltage range.

Abstract: A method includes generating a first current, wherein the first current flows through a first resistor and a first bipolar transistor. A first end of the first resistor is serially connected to an emitter-collector path of the first bipolar transistor, and a second end of the resistor is connected to an input of an operational amplifier. A second current is generated to flow through a second resistor that is connected to the input of the operational amplifier. An emitter of a second bipolar transistor is connected to a base of the first bipolar transistor, wherein a base and a collector of the second bipolar transistor are connected to VSS. The first and the second currents are added to generate a third current, which is mirrored to generate a fourth current proportional to the third current. The fourth current is conducted through a third resistor to generate an output reference voltage.

Abstract: A current cell array includes a number of current cell groups arranged such that they extend in a first direction. Each of the current cell groups is identified by a first identifier that increases in a direction of a gradient across the current cell array. A number of current cells are included in each of the current cell groups. Each of the current cells is identified by a respective second identifier that increases in the direction of the gradient across the current cell array. The current cells are positioned in the current cell groups based on the first and second identifiers.

Abstract: A circuit includes an operational amplifier including a first input and a second input. A first resistor has a first end coupled to the first input. A first bipolar transistor includes a first emitter coupled to a second end of the first resistor, and a first base. A second bipolar transistor includes a second emitter coupled to the second input, and a second base. A third bipolar transistor includes a third emitter coupled to the first base, a first collector, and a third base connected to the first collector. A fourth bipolar transistor includes a fourth emitter coupled to the second base, a second collector, and a fourth base connected to the second collector. A second resistor is coupled to the first input, wherein the second resistor is parallel to the first resistor and the first bipolar transistor.

Abstract: A driver utilizes selective biasing of the terminal of an operational amplifier to reduce offset in the operational amplifier output. Each operational amplifier input includes a differential input pair of transistors including a NMOS transistor and PMOS transistor. At low and high ends of the input voltage range these transistors are selectively and individually coupled to either a standard input or biased to be on so as to contribute offset for offset compensation. The transistors are biased in a conventional manner for input voltages between the low and high ends of the voltage range.