Abstract: A method and apparatus are provided for efficiently managing hot spots in a resource managed computer system. The system utilizes a controller, a series of requestor groups, and a series of loan registers. The controller is configured to allocate and is configured to reallocate resources among the requestor groups to efficiently manage the computer system. The loan registers account for reallocated resources such that intended preallocation of use of shared resources is closely maintained. Hence, the computer system is able to operate efficiently while preventing any single requestor or group of requestors from monopolizing shared resources.

Abstract: A method, system, and product in a data processing system are disclosed for testing a switched area network device having a standardized serial fabric interconnect and that includes logic modules. The device includes test mode logic. A test command is received within the test mode logic via the standardized serial fabric interconnect from an external tester. The test command is then executed by the test mode logic, and a result of the test is then transmitted to the tester via the standardized serial fabric interconnect.

Abstract: A bus bridge with a pool of buffers sets including first and second buffer sets. The bridge includes steering logic for directing transactions issued by a first peripheral device to the first buffer set and transactions issued by the second peripheral device to the second buffer set. The bus bridge is configured to pull posted memory write transactions ahead of a delayed read completion transaction in the first buffer set in response to identifying the first peripheral device as a target of a read request issued by a processor. In one embodiment, the bus bridge is further configured to receive first and second device select signals from the first and second peripheral devices respectively. In this embodiment, the device select signals indicate the target of the read request issued by the processor.

Abstract: A bus bridge including a buffer pool and steering logic where the buffer pool is organized as a plurality of buffers sets including at least first and second buffer sets and the steering logic is adapted to store transactions originating with a first peripheral device in the first buffer set and transactions originating with a second peripheral device in the second buffer set. Transactions may arrive via a secondary bus, such as a PCI bus, coupled to the bus bridge. The bridge further allows relaxed transaction ordering rules compared to conventional PCI transaction ordering rules by identifying transactions by grant signals and thus allows steering of transactions from the first and second devices to first and second buffer sets respectively. The bridge is suitably adapted for combining or merging two or more transactions within each buffer set. Each buffer set preferably includes one or more buffers for temporarily storing transactions arriving from the secondary bus and bound for a primary bus.

Abstract: A bus bridge including a buffer pool comprised of a first and a second buffer sets. The first and second buffer sets are associated with first and second peripheral devices respectively. The bridge is configured to receive an interrupt and identify the interrupt source. A buffer set associated with the interrupt source is selected and transactions in the selected buffer set flushed prior to forwarding the interrupt to a processor. The bridge is preferably configured to identify the interrupt source by receiving a first interrupt signal from the first peripheral device and a second interrupt signal from the second peripheral device. Preferably, the bridge is configured to flush the transactions by pushing them into system memory via a primary bus such as a host bus of a processor.

Abstract: A bus bridge coupled between primary and secondary busses including a buffer pool with first and second buffer sets and steering logic configured to direct transactions received from first and second peripheral devices to the first and second buffer sets respectively. The bridge is configured to push posted memory write transactions posted in the first buffer set onto the primary bus ahead of and in response to a read request transaction from the first peripheral device while leaving transactions in the second buffer set unaffected. In one embodiment, the steering logic is configured to receive first and second grant signals produced by arbitration logic of the bridge. The first and second grant signals indicate mastership of the secondary bus and the source of a subsequent transaction to be received via the secondary bus. The bridge and the secondary bus are suitably compliant with the PCI protocol. The primary bus may be the host bus of a processor unit or a peripheral bus such as a PCI bus.

Abstract: Interrupts from an I/O subsystem are first directed to a single processor in a multiple superscalar processor data processing system. If an interrupt load on the processor is sufficiently high, the interrupt is sent (offloaded) to a second specific processor. The process continues throughout all superscalar processors in the data processing system and each processor builds interrupt prediction data corresponding to the interrupt load. A threshold counter may be added to the logic so offloading does not take place until a specified number of interrupts are queued within that specific processor, thus providing a fixed level of prediction data. Some processors may be left out of the offload string so they are not disturbed by an interrupt.

Abstract: The system I/O interface and its data structure are designed to minimize the host CPU utilization in driving an adapter. The interface is also designed to reduce the system interference in processing I/O requests. To eliminate the need of using PIO instructions, the command/status blocks for exchanging messages between the system and the adapter reside in the system memory. The data structure is designed to avoid "share write" entries in order to further minimize the overhead of maintaining each coherency when updating an entry in the cache either concurrently or sequentially by both adapter and system CPU. Further, the data structure of the control and status blocks is resided in the system memory. The system CPU uses STORE instruction to prepare control blocks and LOAD instruction to read from completion status blocks; while the adapter will rely on its DMA engine to move data to/from system memory in accessing control/status blocks.

Abstract: The present invention is a method and system for improving resource utilization in a connection management system. The present invention alleviates the resource contention and resource under-utilization problems, and avoids the problem of contamination from the late arrival of delayed packets to a new connection which utilizes the same resources used in a preview connection. The method includes transferring data by using the connection resources from the server; determining if an error occurred during the transfer of data; if an error is not detected, returning the connection resources to the server; and if an error is detected, indicating the existence of the error with a status bit and waiting a predetermined period of time prior to returning the connection resources to the server.

Abstract: A network adaptor for receiving and processing Asynchronous Transfer Mode cells within a computer network is disclosed. The network adaptor includes a raw cell buffer, a control table, several Direct Memory Access buffers, and a Direct Memory Access controller. The raw cell buffer is utilized for receiving Asynchronous Transfer Mode cells from the computer network. The control table includes a multiple of virtual circuit identifier entries. When a corresponding virtual circuit identifier of the Asynchronous Transfer Mode cell is found in one of the multiple of virtual circuit identifier entries within the control table, one of the several Direct Memory Access buffers is set to receive the Asynchronous Transfer Mode cell.

Abstract: The present invention provides a system that selectively allows an arbitration cycle to occur only when specific data is ready for transfer. That is, a flag register is provided and its output is ANDed with a bus request signal from a bus device. An arbiter will accept a bus request and initiate an arbitration cycle only when the state of a bit in the flag register indicates that actual completion data exists for the requesting device.

Abstract: An extension to an I/O bus and bridge chip is provided which allows higher speed operations. This includes control logic which switches between different data transfer speeds. A host bridge interconnects a system bus with an I/O bus. Included in the host bridge is both a high frequency and low frequency clock. The bridge chip normally operates at the lower frequency and initiates communication with the I/O at this low frequency. If the I/O device is capable of operating at a higher frequency, then a control signal is transmitted from the I/O device to the bridge chip. In response to the receipt of this signal, control logic in the bridge chip causes the higher frequency clock in the bridge chip to be activated such that the host bridge, bus and I/O device are all then operating at the higher frequency.

Abstract: A method, system and program for distributing data to a first node in a parallel database system from a plurality of existing nodes. First, a minimal sufficient number of communication buffers necessary to guarantee that a table scan operation in each of the existing nodes will execute without stopping is determined. Once calculated, the minimal sufficient number of communication buffer is allocated in the memory associated with each of the existing nodes. Thus, data from each of the plurality of existing nodes to the first node can be redistributed without interruption. Unless the redistribution process has a default set of data to be redistributed, which data from which data tables in each of the plurality of existing nodes is to be distributed to the first node must be determined. The first node may either be a new node which must be registered within the parallel database system, or an existing node within an imbalanced parallel database system which has excess capacity.

Abstract: A method for record searching in a database within a computer system are disclosed. The computer system includes a main processor, a main memory, and a peripheral storage device having a secondary processor. In accordance with the method of the present invention, a command block specifying a search string for record searching in at least one database table of the database is prepared. Subsequently, the command block is issued from the main processor to the secondary processor within the peripheral storage device of the computer system. The secondary processor within the peripheral storage device is then utilized to read the database table(s) into a memory within the peripheral storage device, in response to a receipt of the command block. The search string in the command block is compared to each record of the database table(s) within the memory of the peripheral storage device to identify all the records therein which contain the search string.