Patents by Inventor Wen Wang

Wen Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10784252
    Abstract: An ESD protection circuit, which protects a subject NMOS transistor coupled between an I/O pad and a ground, includes a first discharge device arranged between the I/O pad and the ground, having a trigger-on voltage that is lower than a breakdown voltage of the subject NMOS transistor; and a gate voltage control device, including a discharge NMOS transistor coupled to the ground and a gate of the subject NMOS transistor; a first PMOS transistor connected to the gate of the subject NMOS transistor and a connection node; and a first NMOS transistor connected to the connection node and the ground. The connection node is connected to the gate of the discharge NMOS transistor, and the gate of the first PMOS transistor and the gate of the first NMOS transistor are connected to each other.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: September 22, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang Huang, Li-Fan Chen, Chih-Hsuan Lin, Yu-Kai Wang, Hung-Wei Chen, Ching-Wen Wang, Ting-You Lin, Chun-Chih Chen
  • Patent number: 10783955
    Abstract: A circuit includes a column of memory cells, a first read data line coupled exclusively with a first subset of memory cells of the column of memory cells, a second read data line coupled exclusively with a second subset of memory cells of the column of memory cells, and a plurality of read word lines. Each read word line of the plurality of read word lines is coupled with a memory cell of the first subset of memory cells and with a memory cell of the second subset of memory cells.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: September 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Li-Wen Wang, Yen-Huei Chen, Hung-Jen Liao
  • Publication number: 20200296149
    Abstract: The present disclosure discloses a video description generation method and apparatus, a video playing method and apparatus, and a computer-readable storage medium. The method includes: extracting video features, and obtaining a video feature sequence corresponding to video encoding moments in a video stream; encoding the video feature sequence by using a forward recurrent neural network and a backward recurrent neural network, to obtain a forward hidden state sequence and a backward hidden state sequence corresponding to each video encoding moment; and positioning, according to the forward hidden state sequence and the backward hidden state sequence, an event corresponding to each video encoding moment and an interval corresponding to the event at the video encoding moment, thereby predicting a video content description of the event.
    Type: Application
    Filed: May 28, 2020
    Publication date: September 17, 2020
    Applicant: Tencent Technology (Shenzhen) Company Limited
    Inventors: Jing Wen WANG, Wen Hao JIANG, Lin MA, Wei LIU
  • Publication number: 20200273706
    Abstract: Embodiments of wafer bonding method and structures thereof are disclosed. The wafer bonding method can include performing a plasma activation treatment on a front surface of a first and a front surface of a second wafer; performing a silica sol treatment on the front surfaces of the first and the second wafers; performing a preliminary bonding process of the first and second wafer; and performing a heat treatment of the first and the second wafers to bond the front surface of the first wafer to the front surface of the second wafers.
    Type: Application
    Filed: May 8, 2020
    Publication date: August 27, 2020
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Shuai GUO, Jia Wen WANG, Tao Tao DING, Rui Yuan XING, Xiao Jin WANG, Jia You WANG, Chun Long LI
  • Patent number: 10755713
    Abstract: A method for assisting a user with one or more desired tasks is disclosed. For example, an executable, generic language understanding module and an executable, generic task reasoning module are provided for execution in the computer processing system. A set of run-time specifications is provided to the generic language understanding module and the generic task reasoning module, comprising one or more models specific to a domain. A language input is then received from a user, an intention of the user is determined with respect to one or more desired tasks, and the user is assisted with the one or more desired tasks, in accordance with the intention of the user.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 25, 2020
    Assignee: SRI International
    Inventors: Osher Yadgar, Neil Yorke-Smith, Bart Peintner, Gokhan Tur, Necip Fazil Ayan, Michael J. Wolverton, Girish Acharya, Venkatarama Satyanarayana Parimi, William S. Mark, Wen Wang, Andreas Kathol, Regis Vincent, Horacio E. Franco
  • Patent number: 10755768
    Abstract: A semiconductor memory device includes: a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; a column of segments, each segment including bit cells; each of the bit cells including a latch circuit and first and second pass gates connecting the corresponding LWB and LWB_bar lines to the latch circuit; and a distributed write driving arrangement. The distributed write driving arrangement includes: a global write driver including a first inverter connected between the GWB line and the LWB line, and a second inverter connected between the GWB_bar line and the LWB_bar line; and a local write driver included at an interior of each segment, each local write driver including a third inverter connected between the GWB line and the LWB line; and a fourth inverter connected between the GWB_bar line and the LWB_bar line.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Li-Wen Wang, Jonathan Tsung-Yung Chang, Yen-Huei Chen
  • Publication number: 20200264598
    Abstract: A method, computer system, and a computer program product for predictive maintenance is provided. The present invention may include recording, using an autonomous robot moving along a surface through a plurality of positions in a room, a plurality of data associated with an under-floor appliance provided beneath the surface of the room. The present invention may also include calculating, based on the recorded plurality of data associated with the under-floor appliance provided beneath the surface of the room, a material composition associated with the plurality of positions in the room. The present invention may further include generating, based on the calculated material composition associated with the plurality of positions in the room, a layout diagram for visualizing a layout of the under-floor appliance provided beneath the surface of the room.
    Type: Application
    Filed: February 20, 2019
    Publication date: August 20, 2020
    Inventors: Hao Sheng, Rong Fu, Kang Zhang, Jian Dong Yin, Zhuo Cai, Wen Wang
  • Patent number: 10748851
    Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first and a second semiconductor structures. The first semiconductor structure includes a first interconnect layer including first interconnects. At least one first interconnect is a first dummy interconnect. The first semiconductor structure further includes a first bonding layer including first bonding contacts. Each first interconnect is in contact with a respective first bonding contact. The second semiconductor structure includes a second interconnect layer including second interconnects. At least one second interconnect is a second dummy interconnect. The second semiconductor structure further includes a second bonding layer including second bonding contacts. Each second interconnect is in contact with a respective second bonding contact. The semiconductor device further includes a bonding interface between the first and second bonding layers.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: August 18, 2020
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Tao Wang, Si Ping Hu, Jia Wen Wang, Shi Qi Huang, Jifeng Zhu, Jun Chen, Zi Qun Hua
  • Publication number: 20200247761
    Abstract: The present invention related to novel sulfonamides or amides as TLR-4 antagonists, and pharmaceutical formulations containing the same and the methods of use thereof. Uses of the present novel sulfonamides or amides include, but are not limited to, the prophylaxis and/or treatment of autoimmune, inflammation, or infection related disorders.
    Type: Application
    Filed: January 25, 2018
    Publication date: August 6, 2020
    Applicant: TAIWANJ PHARMACEUTICALS CO., LTD
    Inventors: Syaulan S. YANG, Kuang-Yuan LEE, Meng-Hsien LIU, Ming-Yu HSIAO, Huang-Kai PENG, Chiung-Wen WANG, Edwin SC WU, Peter JS CHIU
  • Publication number: 20200243455
    Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first and a second semiconductor structures. The first semiconductor structure includes a first interconnect layer including first interconnects. At least one first interconnect is a first dummy interconnect. The first semiconductor structure further includes a first bonding layer including first bonding contacts. Each first interconnect is in contact with a respective first bonding contact. The second semiconductor structure includes a second interconnect layer including second interconnects. At least one second interconnect is a second dummy interconnect. The second semiconductor structure further includes a second bonding layer including second bonding contacts. Each second interconnect is in contact with a respective second bonding contact. The semiconductor device further includes a bonding interface between the first and second bonding layers.
    Type: Application
    Filed: March 4, 2019
    Publication date: July 30, 2020
    Inventors: Tao Wang, Si Ping Hu, Jia Wen Wang, Shi Qi Huang, Jifeng Zhu, Jun Chen, Zi Qun Hua
  • Publication number: 20200243473
    Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first and a second semiconductor structures. The first semiconductor structure includes a first interconnect layer including first interconnects. The first semiconductor structure further includes a first bonding layer including first bonding contacts. Each first interconnect is in contact with a respective first bonding contact. The second semiconductor structure includes a second interconnect layer including second interconnects. The second semiconductor structure further includes a second bonding layer including second bonding contacts. At least one second bonding contact is in contact with a respective second interconnect. At least another second bonding contact is separated from the second interconnects. The semiconductor device further includes a bonding interface between the first and second bonding layers.
    Type: Application
    Filed: March 4, 2019
    Publication date: July 30, 2020
    Inventors: Tao Wang, Si Ping Hu, Jia Wen Wang, Shi Qi Huang, Jifeng Zhu, Jun Chen, Zi Qun Hua
  • Patent number: 10720440
    Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: July 21, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Wen Wang, Hsiang-Chen Lee, Wen-Peng Hsu, Kuo-Lung Li, Meng-Chun Chen, Zi-Jun Liu, Ping-Chia Shih
  • Patent number: 10719696
    Abstract: A computational device stores a plurality of audiovisual recordings comprising presentations made during a videoconference and visual reactions of attendees. A data collection model is generated at a conference level, a topic level, and an attendee level. A level of interest of an attendee to a topic or a speaker is determined from data collected in the data collection model at the conference level, the topic level and the attendee level. The determined level of interest of attendees to topics or speakers is displayed in a data structure.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: July 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Wen Wang, Yan Bin Fu, Shuang Yin Liu, Yi Wu, Qing Jun Gao
  • Publication number: 20200213708
    Abstract: A headband adjustment structure includes a rotary adjusting assembly, a wearing unit having an adjustable accommodation space, a cable management module located between the wearing unit and the rotary adjusting assembly for carrying a cable, an adjustment gear set linkably coupled to the cable management module, and a driving rotation shaft set passing through the wearing unit and the cable management module, and linkably coupled to the wearing unit and the adjustment gear set, and coaxially connected to the rotary adjusting assembly. When the rotary adjusting assembly rotates the driving rotation shaft set, the driving rotation shaft set synchronously moves the wearing unit to adjust the adjustable accommodation space, and moves the cable management module through the adjustment gear set. The amount of the movement of the cable management module is different from that of the wearing unit.
    Type: Application
    Filed: April 18, 2019
    Publication date: July 2, 2020
    Inventors: Chun-Wen Wang, Ko-Chun Wang, Chao Chien, Kok-Kan Chan, Chien-Yu Hou, Chun-Lung Chen
  • Patent number: 10700817
    Abstract: A multi-member Bluetooth device includes: a main Bluetooth circuit capable of bidirectionally communicating with a remote Bluetooth device through a first Bluetooth communication circuit; and an auxiliary Bluetooth circuit capable of communicating with the main Bluetooth circuit through a data transmission circuit. While the main Bluetooth circuit utilizes the first Bluetooth communication circuit to communicate with the remote Bluetooth device, the auxiliary Bluetooth circuit utilizes a second Bluetooth communication circuit to sniff packets transmitted from the remote Bluetooth device. When detected that the auxiliary Bluetooth circuit has missed packets transmitted from the remote Bluetooth device, the main Bluetooth circuit transmits missing packets of the auxiliary Bluetooth circuit to the auxiliary Bluetooth circuit through the data transmission circuit.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: June 30, 2020
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Yi-Cheng Chen, Kuan-Chung Huang, Chin-Wen Wang, Pei-Yuan Hsieh, Hou Wei Lin
  • Patent number: 10699534
    Abstract: A real-time streaming system for a machine is provided, including at least one camera, being adapted for shooting a real-time image of the machine, the machine being adapted for being remote controlled by an player; a cloud processing unit, being communicated with the at least one camera and adapted for communicable with the machine through an internet, the cloud processing unit including an image server, the image server being adapted for being communicable with a plurality of viewer ends through the internet so that the plurality of viewer ends receive the real-time image; wherein the machine provides a peer-to-peer network (P2P) connection, the player receives the real-time image from the at least one camera in the peer-to-peer network (P2P) connection.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: June 30, 2020
    Inventors: Jian-Hong Wang, Hsing-Wen Wang
  • Publication number: 20200199325
    Abstract: This invention relates to the field of contaminated plastic waste decomposition. More specifically, the invention comprises methods and systems to decompose contaminated plastic waste and transform it into value-added products.
    Type: Application
    Filed: December 17, 2019
    Publication date: June 25, 2020
    Applicant: BIOCELLECTION INC.
    Inventors: Jia Yun YAO, Yu Wen WANG, Tapaswy MUPPANENI, Ruja SHRESTHA, Jennifer LE ROY, Garret D. FIGULY
  • Patent number: 10685870
    Abstract: An opening is formed within a dielectric material overlying a semiconductor substrate. The opening may comprise a via portion and a trench portion. During the manufacturing process a treatment chemical is placed into contact with the exposed surfaces in order to release charges that have built up on the surfaces. By releasing the charges, a surface change potential difference is reduced, helping to prevent galvanic corrosion from occurring during further manufacturing.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: June 16, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Wen Hsu, Ming-Che Ku, Neng-Jye Yang, Yu-Wen Wang
  • Patent number: 10679854
    Abstract: Embodiments of wafer bonding method and structures thereof are disclosed. The wafer bonding method can include performing a plasma activation treatment on a front surface of a first and a front surface of a second wafer; performing a silica sol treatment on the front surfaces of the first and the second wafers; performing a preliminary bonding process of the first and second wafer; and performing a heat treatment of the first and the second wafers to bond the front surface of the first wafer to the front surface of the second wafers.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: June 9, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Shuai Guo, Jia Wen Wang, Tao Tao Ding, Rui Yuan Xing, Xiao Jin Wang, Jia You Wang, Chun Long Li
  • Patent number: 10676668
    Abstract: For a metal gate replacement integration scheme, the present disclosure describes removing a polysilicon gate electrode with a highly selective wet etch chemistry without damaging surrounding layers. For example, the wet etch chemistry can include one or more alkaline solvents with a steric hindrance amine structure, a buffer system that includes tetramethylammonium hydroxide (TMAH) and monoethanolamine (MEA), one or more polar solvents, and water.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Neng-Jye Yang, Kuo Bin Huang, Ming-Hsi Yeh, Shun Wu Lin, Yu-Wen Wang, Jian-Jou Lian, Shih Min Chang