Abstract: A memory device includes a resistor and a controller chip. The controller chip includes a first controller, a second controller, a first set of input/output (I/O) circuits, a second set of I/O circuits, a first calibration circuit, a second calibration circuit, and an arbitration circuit. The first controller transmits a first controller calibration request. The second controller transmits a second controller calibration request. The arbitration circuit instructs the first calibration circuit to perform a first controller calibration on the first set of I/O circuits using the resistor in response to the first controller calibration request, and instructs the second calibration circuit to perform a second controller calibration on the second set of I/O circuits using the resistor in response to the second controller calibration request. A first time interval of performing the first controller calibration and a second time interval of performing the second controller calibrations are non-overlapping.

Abstract: The present disclosure provides a method and an electronic apparatus for masking data on an electronic document. The method is performed by the electronic apparatus and includes: displaying the electronic document on a user interface; causing at least one analysis module to perform at least one analysis on the electronic document and a plurality of strings of the electronic document and output a first string among the plurality of strings and first position information associated with the first string according to a result of the at least one analysis; obtaining the first string and the first position information from the at least one analysis module; and generating, based on the first position information and the first string, a first masking object to mask the first string on the electronic document.

Abstract: There is provided a method for determining text blocks of a PDF text, including: acquiring information of characters of the PDF text; performing an initial division according to gap outliers of the PDF text in a transverse direction and a longitudinal direction, and adding block tags of first text blocks to the information of characters; sequentially processing inaccurate lines and inaccurate words in each first text block according to baselines of characters, character lengths, character spaces and character indexes; performing a baseline arrangement on lines of the PDF text; sequentially comparing two lines to form second text blocks; and sequentially comparing two second text blocks to identify whether to perform a secondary merging and a secondary division.

Abstract: A circuit board detection device includes a base, a stage assembly, a first gantry support, and a first probe assembly. The stage assembly is arranged on the base and includes a linear drive module, a rotary motor, and a platform. The platform is configured to carry a circuit board and can be driven by the linear drive module to move along a first axial direction. The platform can also be driven by the rotary motor to rotate relative to a first rotation axis. The first gantry support is fixed on the base and includes a first beam. The first beam extends along a second axial direction perpendicular to the first axial direction to span over the linear drive module, and includes a first probe guide rail. The first probe assembly is arranged on the first probe guide rail to be movable along the second axial direction.

Abstract: There is provided a method for processing tables in a PDF file, including: parsing the PDF file to obtain coordinates of start points and end points of all transverse line sections and longitudinal line sections; obtaining coordinates of crosspoints of all line sections and recording coordinates of line sections that form the crosspoints; calculating all unit grids according to the coordinates of the crosspoints and the coordinates of the line sections; and filling every character respectively into a corresponding unit grid according to character coordinates obtained in parsing the PDF file.

Abstract: There is provided a device for editing a PDF file, including a display, a non-volatile storage medium, a memory and a processor. The non-volatile storage medium stores a computer program. The memory provides an environment for operations of the computer program in the non-volatile storage medium. The processor runs the computer program to parse the PDF file to obtain information of characters, generate character sets according to features of the characters, generate line sets according to heights and horizontal positions of the character sets, generate paragraph sets according to a height and a horizontal position of each line of the line sets, generate text region sets according a height and a horizontal position of each paragraph of the paragraph sets, and control the display to show the text region sets in the PDF file as editable text regions.

Abstract: A memory device includes a resistor and a controller chip. The controller chip includes a first controller, a second controller, a first set of input/output (I/O) circuits, a second set of I/O circuits, a first calibration circuit, a second calibration circuit, and an arbitration circuit. The first controller transmits a first controller calibration request. The second controller transmits a second controller calibration request. The arbitration circuit instructs the first calibration circuit to perform a first controller calibration on the first set of I/O circuits using the resistor in response to the first controller calibration request, and instructs the second calibration circuit to perform a second controller calibration on the second set of I/O circuits using the resistor in response to the second controller calibration request. A first time interval of performing the first controller calibration and a second time interval of performing the second controller calibrations are non-overlapping.

Abstract: This disclosure provides a method and a user apparatus for generating and applying a translation marker, and the method is performed by the user apparatus and comprises: opening an electronic document on a user operation interface; selecting at least one text string in the electronic document according to a first triggering event; and when a translation option is detected to be selected, performing the following steps: generating a code corresponding to the selected text string by using an operation function; and displaying a first translated text string of the first translation record on the user operation interface and generating a first translation marker associated with the first translated text string on the electronic document when it is determined that a first translation record associated with the code exists in the user apparatus.

Abstract: The present invention provides a control method of multiple memory devices, wherein the multiple devices comprise a first memory device and a second memory device, and the control method includes the steps of: determining a first operation timing and a second operation timing according to at least a first command signal that a first memory controller needs to send to the first memory device; controlling the first memory controller to send the first command signal to the first memory device at the first operation timing; and controlling the second memory controller to send the second command signal to the second memory device at the second operation timing.

Abstract: A method for simultaneously accessing a first DRAM device and a second DRAM device includes the steps of: in an active phase, generating a first signal at a first pad, wherein the first signal is provided for the first DRAM device to select a first memory bank group, and the first signal is not for the second DRAM device to select any memory bank group; and generating a second signal at the first pad, wherein the second signal is provided for the first DRAM device to select the first bank group, and the second signal and the first signal correspond to a same digital value.

Abstract: A laser module, comprising: a loading board; an edge emitting laser component arranged on the loading board, and the edge emitting laser component emits a first laser beam; a reflecting component arranged in front of the edge emitting laser component on the loading board for the first laser beam to be reflected vertically, and the edge emitting laser component and reflecting component become a laser emitting module; and a laser receiving module arranged closed to the edge emitting laser component on the loading board to receive the first laser beam reflected from above.

Abstract: The present invention provides a control method of multiple memory devices, wherein the multiple devices comprise a first memory device and a second memory device, and the control method includes the steps of: determining a first operation timing and a second operation timing according to at least a first command signal that a first memory controller needs to send to the first memory device; controlling the first memory controller to send the first command signal to the first memory device at the first operation timing; and controlling the second memory controller to send the second command signal to the second memory device at the second operation timing.

Abstract: A method of memory time division control for a memory system comprising a plurality of memory controllers and memory devices is disclosed. The method comprises assigning a first operation timing to a first memory controller of the plurality of memory controllers and assigning a second operation timing to a second memory controller of the plurality of memory controllers, wherein the first operation timing is interleaved with the time of the second operation timing, transmitting a first chip select signal generated according to the first command signal, to a first memory device of the plurality of memory devices, and transmitting a second chip select signal generated according to the second command signal, to a second memory device of the plurality of memory devices.

Abstract: A control method of a memory system is disclosed. The memory system includes a controller, an interface and a memory. The interface is coupled to the controller, and the memory is coupled to the controller through the interface. The control method includes the controller sending a clock signal to the memory through the interface, and the controller sending an access command to the memory through the interface to access data at an access address of the memory. The clock signal has a clock period. A time span for the controller to send the access command to the memory is substantially 1.5 clock periods.

Abstract: A method of memory time division control for a memory system comprising a plurality of memory controllers and memory devices is disclosed. The method comprises assigning a first operation timing to a first memory controller of the plurality of memory controllers and assigning a second operation timing to a second memory controller of the plurality of memory controllers, wherein the first operation timing is interleaved with the time of the second operation timing, transmitting a first chip select signal generated according to the first command signal, to a first memory device of the plurality of memory devices, and transmitting a second chip select signal generated according to the second command signal, to a second memory device of the plurality of memory devices.

Abstract: The present disclosure is related to a memory circuit. The memory includes a memory controller and a memory interface coupled between the memory controller and a memory device. The memory controller is configured to generate an output signal that is transmitted to the memory device. The memory interface includes a feedback path configured to receive the output signal and generates a feedback signal in response to the output signal and a variable reference voltage. The memory controller further includes a data register so as to sample the feedback signal in response to a clock signal having a phase with an adjustable shift.

Abstract: A method for simultaneously accessing a first DRAM device and a second DRAM device includes the steps of: in an active phase, generating a first signal at a first pad, wherein the first signal is provided for the first DRAM device to select a first memory bank group, and the first signal is not for the second DRAM device to select any memory bank group; and generating a second signal at the first pad, wherein the second signal is provided for the first DRAM device to select the first bank group, and the second signal and the first signal correspond to a same digital value.

Abstract: A laser module, comprising: a loading board; an edge emitting laser component arranged on the loading board, and the edge emitting laser component emits a first laser beam; a reflecting component arranged in front of the edge emitting laser component on the loading board for the first laser beam to be reflected vertically, and the edge emitting laser component and reflecting component become a laser emitting module; and a laser receiving module arranged closed to the edge emitting laser component on the loading board to receive the first laser beam reflected from above.

Abstract: In certain aspects, the invention provides a novel crystalline form of olaparib (4-[(3-[(4-cyclopropylcarbonyl)piperazin-4-yl]carbonyl)-4-fluorophenyl]methyl(2H)phthalazin-1-one). In related aspects, the invention provides a processe for preparing the novel crystalline form of olaparib. The process includes forming a solution comprising crude olaparib and an organic solvent; adding the solution to an anti-solvent to form a slurry comprising a precipitate; isolating the precipitate; and drying the precipitate to obtain a crystalline form III of olaparib.

Abstract: The present disclosure is related to a memory circuit. The memory includes a memory controller and a memory interface coupled between the memory controller and a memory device. The memory controller is configured to generate an output signal that is transmitted to the memory device. The memory interface includes a feedback path configured to receive the output signal and generates a feedback signal in response to the output signal and a variable reference voltage. The memory controller further includes a data register so as to sample the feedback signal in response to a clock signal having a phase with an adjustable shift.