Patents by Inventor Wen Yang
Wen Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11949016Abstract: A method of fabricating a device includes providing a fin element in a device region and forming a dummy gate over the fin element. In some embodiments, the method further includes forming a source/drain feature within a source/drain region adjacent to the dummy gate. In some cases, the source/drain feature includes a bottom region and a top region contacting the bottom region at an interface interposing the top and bottom regions. In some embodiments, the method further includes performing a plurality of dopant implants into the source/drain feature. In some examples, the plurality of dopant implants includes implantation of a first dopant within the bottom region and implantation of a second dopant within the top region. In some embodiments, the first dopant has a first graded doping profile within the bottom region, and the second dopant has a second graded doping profile within the top region.Type: GrantFiled: May 13, 2021Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Hao Lin, Chih-Chuan Yang, Chih-Hsuan Chen, Bwo-Ning Chen, Cha-Hon Chou, Hsin-Wen Su, Chih-Hsiang Huang
-
Patent number: 11948197Abstract: An exemplary system according to the present disclosure comprises a computing device that in operation, causes the system to receive financial product or financial portfolio data, map the financial product to a risk factor, execute a risk factor simulation process involving the risk factor, generate product profit and loss values for the financial product or portfolio profit and loss values for the financial portfolio based on the risk factor simulation process, and determine an initial margin for the financial product. The risk factor simulation process can be a filtered historical simulation process.Type: GrantFiled: September 12, 2022Date of Patent: April 2, 2024Assignee: Intercontinental Exchange Holdings, Inc.Inventors: Atsushi Maruyama, Boudewijn Duinstra, Christian A. M. Schlegel, Daniel R. de Almeida, Fernando V. Cerezetti, Gabriel E. S. Medina, Ghais Issa, Iddo Yekutieli, Jerome M. Drean, Marcus Keppeler, Rafik Mrabet, Stephen R. Pounds, Wen Jiang, Yanyan Hu, Yunke Yang
-
Patent number: 11949174Abstract: A broadband fifth-generation (5G) circularly polarized filtering antenna includes a reflecting plate, a first dielectric substrate, a second dielectric substrate, a third dielectric substrate, a fourth dielectric substrate, a feed line with a phase adjustment function print on one surface of the first dielectric substrate, a ground with a chair-like groove on an other surface of the first dielectric substrate, a first rectangular radiating unit, a second rectangular radiating unit, a first metal transmission strip group and a second metal transmission strip group.Type: GrantFiled: July 5, 2023Date of Patent: April 2, 2024Assignee: ANHUI UNIVERSITYInventors: Yingsong Li, Wen Li, Zhixiang Huang, Lixia Yang
-
Publication number: 20240102154Abstract: A vacuum processing apparatus (110) for deposition of a material on a substrate is provided. The vacuum processing apparatus (110) includes a vacuum chamber comprising a processing area (111); a deposition apparatus (112) within the processing area (111) of the vacuum chamber; a cooling surface (113) inside the vacuum chamber; and one or more movable shields (220) between the cooling surface (113) and the processing area (111).Type: ApplicationFiled: February 24, 2020Publication date: March 28, 2024Inventors: Chun Cheng CHEN, Hung-Wen CHANG, Shin-Hung LIN, Chi-Chang YANG, Christoph MUNDORF, Thomas GEBELE, Jürgen GRILLMAYER
-
Publication number: 20240099920Abstract: A method for controlling a device for automatically adjusting an airway opening body position is provided. The device includes a horizontal base plate, a head support block, a back support plate, a neck support apparatus, a head cover assembly, and a programmable logic controller (PLC). The neck support apparatus is positioned between the head support block and the back support plate. The PLC is configured to controls a stroke of an electric cylinder according to the following equations: ?=1.235?+?, and ?=KX+B+C, where ? is a body position angle, the body position angle is an angle between a positive projection line of a connecting line from a mandibular angle to an external acoustic meatus on a symmetrical surface of a human body and the back support plate, and ? is a preset value ranging from 90° to 100°.Type: ApplicationFiled: November 14, 2022Publication date: March 28, 2024Inventors: XIANG-MEI YANG, MIN-YUE SUN, HONG-MEI CHEN, YAN LUO, JUN WU, JUAN HUANG, DONG-MEI LI, QING ZENG, JING ZHOU, JING WEN, JIN-JIN GUO
-
Patent number: 11942169Abstract: A semiconductor memory device includes a first word line formed over a first active region. In some embodiments, a first metal line is disposed over and perpendicular to the first word line, where the first metal line is electrically connected to the first word line using a first conductive via, and where the first conductive via is disposed over the first active region. In some examples, the semiconductor memory device further includes a second metal line and a third metal line both parallel to the first metal line and disposed on opposing sides of the first metal line, where the second metal line is electrically connected to a source/drain region of the first active region using a second conductive via, and where the third metal line is electrically connected to the source/drain region of the first active region using a third conductive via.Type: GrantFiled: July 20, 2022Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsin-Wen Su, Kian-Long Lim, Wen-Chun Keng, Chang-Ta Yang, Shih-Hao Lin
-
Patent number: 11941572Abstract: Various embodiments are disclosed for providing machine learning routines with peripheral device data to infer driver activity and location. Peripheral device data may be collected on a peripheral device having a machine learning routine executing thereon to infer driver activity and perform improved estimation of driver location. Using driver activity and location estimation, contextually relevant delivery workflow assistance may be automatically provided to a delivery driver or other individual without requiring manual input, thereby improving driver safety and operational efficiency.Type: GrantFiled: March 16, 2021Date of Patent: March 26, 2024Assignee: AMAZON TECHNOLOGIES, INC.Inventors: Ruth Ravichandran, Hebaallah Aly Abdelhalim Aly Ismail, Zheng Wang, Shao-Wen Yang, Yang Pan, David Hung Huynh, Andrey Li, Hoshgeldy Tagangeldyevich Tachmuradov, Steven Larson
-
Patent number: 11944021Abstract: Some embodiments relate to an integrated circuit including one or more memory cells arranged over a semiconductor substrate between an upper metal interconnect layer and a lower metal interconnect layer. A memory cell includes a bottom electrode disposed over the lower metal interconnect layer, a data storage or dielectric layer disposed over the bottom electrode, and a top electrode disposed over the data storage or dielectric layer. An upper surface of the top electrode is in direct contact with the upper metal interconnect layer without a via or contact coupling the upper surface of the top electrode to the upper metal interconnect layer. Sidewall spacers are arranged along sidewalls of the top electrode, and have bottom surfaces that rest on an upper surface of the data storage or dielectric layer.Type: GrantFiled: March 15, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Yang Chang, Wen-Ting Chu
-
Patent number: 11942145Abstract: The present disclosure describes a method for memory cell placement. The method can include placing a memory cell region in a layout area and placing a well pick-up region and a first power supply routing region along a first side of the memory cell region. The method also includes placing a second power supply routing region and a bitline jumper routing region along a second side of the memory cell region, where the second side is on an opposite side to that of the first side. The method further includes placing a device region along the second side of the memory cell region, where the bitline jumper routing region is between the second power supply routing region and the device region.Type: GrantFiled: May 6, 2022Date of Patent: March 26, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Chuan Yang, Jui-Wen Chang, Feng-Ming Chang, Kian-Long Lim, Kuo-Hsiu Hsu, Lien Jung Hung, Ping-Wei Wang
-
Publication number: 20240096630Abstract: Disclosed is a semiconductor fabrication method. The method includes forming a gate stack in an area previously occupied by a dummy gate structure; forming a first metal cap layer over the gate stack; forming a first dielectric cap layer over the first metal cap layer; selectively removing a portion of the gate stack and the first metal cap layer while leaving a sidewall portion of the first metal cap layer that extends along a sidewall of the first dielectric cap layer; forming a second metal cap layer over the gate stack and the first metal cap layer wherein a sidewall portion of the second metal cap layer extends further along a sidewall of the first dielectric cap layer; forming a second dielectric cap layer over the second metal cap layer; and flattening a top layer of the first dielectric cap layer and the second dielectric cap layer using planarization operations.Type: ApplicationFiled: January 12, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Wei Yin, Tzu-Wen Pan, Yu-Hsien Lin, Yu-Shih Wang, Jih-Sheng Yang, Shih-Chieh Chao, Yih-Ann Lin, Ryan Chia-Jen Chen
-
Publication number: 20240097035Abstract: Epitaxial source/drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs, and methods of fabricating the epitaxial source/drain structures, are disclosed herein. An exemplary device includes a dielectric substrate. The device further includes a channel layer, a gate disposed over the channel layer, and an epitaxial source/drain structure disposed adjacent to the channel layer. The channel layer, the gate, and the epitaxial source/drain structure are disposed over the dielectric substrate. The epitaxial source/drain structure includes an inner portion having a first dopant concentration and an outer portion having a second dopant concentration that is less than the first dopant concentration. The inner portion physically contacts the dielectric substrate, and the outer portion is disposed between the inner portion and the channel layer. In some embodiments, the outer portion physically contacts the dielectric substrate.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Inventors: Chen-Ming Lee, I-Wen Wu, Po-Yu Huang, Fu-Kai Yang, Mei-Yun Wang
-
Publication number: 20240097337Abstract: A broadband fifth-generation (5G) circularly polarized filtering antenna includes a reflecting plate, a first dielectric substrate, a second dielectric substrate, a third dielectric substrate, a fourth dielectric substrate, a feed line with a phase adjustment function print on one surface of the first dielectric substrate, a ground with a chair-like groove on an other surface of the first dielectric substrate, a first rectangular radiating unit, a second rectangular radiating unit, a first metal transmission strip group and a second metal transmission strip group.Type: ApplicationFiled: July 5, 2023Publication date: March 21, 2024Inventors: Yingsong LI, Wen LI, Zhixiang HUANG, Lixia YANG
-
Publication number: 20240096985Abstract: Methods and devices including an air gap adjacent a contact element extending to a source/drain feature of a device are described. Some embodiments of the method include depositing a dummy layer, which is subsequently removed to form the air gap. The dummy layer and subsequent air gap may be formed after a SAC dielectric layer such as silicon nitride is formed over an adjacent metal gate structure.Type: ApplicationFiled: November 27, 2023Publication date: March 21, 2024Inventors: I-Wen WU, Chen-Ming LEE, Fu-Kai YANG, Mei-Yun WANG
-
Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
-
Publication number: 20240088004Abstract: A stacked wiring structure includes a first wiring substrate and a second wiring substrate. The first wiring substrate includes a first glass substrate, multiple first conductive through vias penetrating through the first glass substrate, and a first multi-layered redistribution wiring structure disposed on the first glass substrate. The second wiring substrate includes a second glass substrate, multiple second conductive through vias penetrating through the second glass substrate, and a second multi-layered redistribution wiring structure disposed on the second glass substrate. The first conductive through vias are electrically connected to the second conductive through vias. The first glass substrate is spaced apart from the second glass substrate. The first multi-layered redistribution wiring structure is spaced apart from the second multi-layered redistribution wiring structure by the first glass substrate and the second glass substrate.Type: ApplicationFiled: August 21, 2023Publication date: March 14, 2024Applicant: Industrial Technology Research InstituteInventors: Tai-Jui Wang, Jui-Wen Yang, Chieh-Wei Feng, Chih Wei Lu, Hsien-Wei Chiu
-
Patent number: 11928734Abstract: An exemplary system according to the present disclosure comprises a computing device that in operation, causes the system to receive financial product or financial portfolio data, map the financial product to a risk factor, execute a risk factor simulation process involving the risk factor, generate product profit and loss values for the financial product or portfolio profit and loss values for the financial portfolio based on the risk factor simulation process, and determine an initial margin for the financial product. The risk factor simulation process can be a filtered historical simulation process.Type: GrantFiled: April 13, 2022Date of Patent: March 12, 2024Assignee: Intercontinental Exchange Holdings, Inc.Inventors: Atsushi Maruyama, Boudewijn Duinstra, Christian A. M. Schlegel, Daniel R. de Almeida, Fernando V. Cerezetti, Gabriel E. S. Medina, Ghais Issa, Iddo Yekutieli, Jerome M. Drean, Marcus Keppeler, Rafik Mrabet, Stephen R. Pounds, Wen Jiang, Yanyan Hu, Yunke Yang
-
Patent number: 11929567Abstract: A card edge connector includes an insulative housing and two rows of terminals. The insulative housing includes two side walls. The terminals include signal terminals and grounding terminals each having a retaining portion, a contact portion, and a soldering portion. Two adjacent terminals in each row constitutes a terminal pair. The soldering portions of each terminal pair are aligned with each other in a longitudinal direction and the soldering portions of an adjacent terminal pair are deviate from each other in the longitudinal direction so that the soldering portions of the two rows of the terminals are arranged in four rows. The terminal pairs include three types of arrangement and in each arrangement the soldering portions of the ground terminals are placed next to the soldering portions of the signal terminals in the closest way in order to reduce interference during transmission.Type: GrantFiled: January 25, 2022Date of Patent: March 12, 2024Assignees: FOXCONN (KUNSHAN) COMPUTER CONNECTOR CO., LTD., FOXCONN INTERCONNECT TECHNOLOGY LIMITEDInventors: Wen-Jun Tang, Tian Yang
-
Publication number: 20240080918Abstract: In a communication method, a session management function network element initiates a procedure of a first operation for a first session; the session management function network element receives a request to establish user-plane resources for the first session from an access and mobility management function network element in a process of performing the first operation; and the session management function network element determines a subsequent procedure based on the first operation.Type: ApplicationFiled: November 13, 2023Publication date: March 7, 2024Inventors: Linping Yang, Xiange Hu, Wen Hu, Li Qiang
-
Publication number: 20240078441Abstract: A method for knowledge representation and deduction of service logic includes: generating, based on a knowledge representation model, a semantic graph corresponding to conceptual-layer service logic, where the semantic graph includes one or more types of nodes and edges for connecting the one or more types of nodes, and the nodes include at least a node of a variable type; generating, based on the semantic graph and a physical table to which a service object is mapped, an instance graph, where the instance graph includes the nodes and edges in the semantic graph; generating executable code based on a service logic relationship between the nodes in the instance graph; and determining, based on the executable code and a data instance corresponding to a node whose in-degree is 0 in the instance graph, a data instance corresponding to each node in the instance graph.Type: ApplicationFiled: November 9, 2023Publication date: March 7, 2024Inventors: Rong Duan, Kangxing Hu, Wenwen Huang, Yuan Yuan, Wen Peng, Chunxi Liu, Qinjie Yang, Xiaoliang Yin, Shufan Li
-
Publication number: 20240078362Abstract: Machine assisted systems and methods for enhancing the resolution of an IC thermal profile from a system analysis are described. These systems and methods can use a neural network based predictor, that has been trained to determine a temperature rise across an entire IC. The training of the predictor can include generating a representation of two or more templates identifying different portions of an integrated circuit (IC), each template associated with location parameters to position the template in the IC; performing thermal simulations for each respective template of the IC, each thermal simulation determining an output based on a power pattern of tiles of the respective template, the output indicating a change in temperature of a center tile of the respective template relative to a base temperature of the integrated circuit; and training a neural network.Type: ApplicationFiled: November 13, 2023Publication date: March 7, 2024Inventors: Norman CHANG, Hsiming PAN, Jimin WEN, Deqi ZHU, Wenbo XIA, Akhilesh KUMAR, Wen-Tze CHUANG, En-Cih YANG, Karthik SRINIVASAN, Ying-Shiun LI