Abstract: A digital sum variation (DSV) computation method and system is proposed, which is capable of determining the DSV value of a bit stream of channel-bit symbols to thereby find the optimal merge-bit symbol for insertion between each succeeding pair of the channel-bit symbols. This DSV computation method and system is characterized in the use of a Zero Digital Sum Variation (ZDSV) principle to determine the DSV. This DSV computation method and system can find the optimal merge-bit symbol for insertion between each succeeding pair of the channel-bit symbols in a more cost-effective manner with the need for a reduced amount of memory and utilizes a lookup table requiring a reduced amount of memory space for storage so that memory space can be reduced as compared to the prior art. This DSV computation method and system is therefore more advantageous to use than the prior art.

Abstract: A gain calibration device and method for differential push-pull (DPP) tracking error signals in an optical storage system is provided. The gain calibration method processes the synthesized gain (SPPG) of the sub beam in the DPP tracking error signal components with respect to the main beam. The calibration theorem resides in controlling the objective lens of the pick-up head to form a lens-shift or controlling the tilt of the objective lens relative to the optical disc to make the synthesized DPP tracking error signals generate a correspondingly signal variation owing to the optical path deviation. The synthesized gain is calibrated to make the signal variation a minimum value, and the calibrated synthesized gain is the optimum value.

Abstract: The invention provides a decoding circuit and a decoding method of a Viterbi decoder. The decoding circuit of the Viterbi decoder includes a branch metric unit, an add-compare-select unit and a path memory unit. The path memory unit includes a data string controller, a trace write-in register array, an idling register array and a decoding register array. In this invention, a run length limited code is used for effectively solving the problem of generating a complicated trellis diagram after the trellis diagram of the Viterbi decoder is subjected to a longitudinal arrangement. In addition, the register array can perform other operations at different time. Accordingly, a high decoding speed of the Viterbi decoder can be achieved without requiring a lot of registers for data processing.

Abstract: A circuit and method for protecting the run length in RLL (run length limited) code is proposed to correct the illegal run length in an EFM (eight to fourteen modulation) signal. The proposed circuit comprises a sampling unit for sampling a RF signal with a high frequency sampling clock, and generating a high frequency sampling signal. The frequency of the high frequency sampling clock is higher then the frequency of the EFM signal. A detector is employed to receive and to detect the high frequency sampling signal whether there is any illegal run length in the EFM signal, and to generate control signals. Two reference signal generators are employed to generate an ideal front reference signal and an ideal rear reference signal, respectively, corresponding to the control signals. A first difference generator and a second difference generator are employed to generate a first difference and a second difference according to the front and rear reference signals and the high frequency sampling signal, respectively.

Abstract: In a recordable disk recording controller circuit, a data buffer manager receives a command and sends the command to a micro-controller. The micro-controller generates a set of register batches from each command and sends the register data and index of the register batch to a batch register controller. The batch register controller receives the register data and index of the register batch from the micro-controller and stores the received register data and index of the register batch in a batch buffer. The batch register controller retrieves the register batches from the batch buffer and writes the master registers of an encoder controller based on the register index and register data of the register batches after the master registers of the encoder controller are updated into the slave registers of the encoder controller. The encoder controller generates control signals to a recording circuit depending on updated slave registers.

Abstract: An adaptive-selection method for memory access priority control in MPEG processor. The processor has functional modules that include an input interface, a CPU, an audio decoder, a video decoder, an audio processor, a video processor and a memory controller. Each of the modules gains control over the data bus via arbitration by the memory controller for accessing the memory. The access priority of the CPU to the data bus is maintained at a relatively lower level except when the CPU needs to perform parsing on the MPEG compressed data and implementing the initial decoding of the audio compressed data. The use of data bus bandwidth is therefore balanced among all the system resources thereby increasing the overall system performance.

Abstract: Disclosed is a memory control device with partitioned memory control for use on a computer system configured based on a shared main memory architecture. The memory control device comprises a main memory controller connected with two sets of access control buses used respectively for partitioned control of the main memory. The main memory is partitioned into a main system dedicated memory segment and a shared resource memory segment respectively for use by the CPU and the peripheral system. A shared data path circuit is used to control data flow on the buses. When the CPU and the peripheral system both want to gain access to the main memory at the same time, the two sets of buses work independently to respectively connect the CPU to the main system dedicated memory segment and the peripheral system to the shared resource memory segment in the main memory for simultaneous, partitioned access to the main memory.

Abstract: An apparatus for branch detecting a loop operation in a microprocessor. The apparatus includes a register, an ALU port, a predetector, an ALU, a flag generator and a branch detector. The register is provided for storing a loop information. Through the ALU port, the loop information is sent to the predetector and is predetected therein whenever the loop operation is about to proceed. A predetected result is then generated by the predetected and is sent to the branch detector to determine whether the loop operation has to be terminated. The ALU processes the loop information and updates new loop the register at the same time the predetection and detection tasks are performed by the predetector and the branch detector, respectively. The flag generator generates a flag which is independent of the detection and termination of the loop operation.