Abstract: A phase locked loop (PLL) for generating an output signal according to an input signal is disclosed. The PLL of the present invention includes a detector for generating a detection signal according to the logical difference between the input signal and a feedback signal, a signal mixer electrically connected to the detector for generating a control signal according to the detection signal and a mixing reference signal, a filtering device electrically connected to the signal mixer for generating an adjust signal according to the control signal, a controllable oscillator electrically connected to the filtering device for generating the output signal according to the adjust signal, and a frequency divider electrically connected to the controllable oscillator for generating the feedback signal and the mixing reference signal according to the output signal. The frequency of the output signal is at least twice the frequency of the input signal.

Abstract: The present invention is a correcting system for correcting a linear block code generated by coding an original data via a data coding process when a predetermined correction portion of an original data is corrected by a variant correction data. The correcting system comprises a coding module and a correcting module. The coding module is used to code the variant correction data via the data coding process to generate a corresponding variant correction code. The correcting module is used to store the variant correction code and calculate the variant correction code and the linear block code to generate a substitute code to substitute the linear block code. Therefore, if the data is modified after an optical recording system has completed coding the data, the optical recording system could add the substitute code to generate the renewed linear block code, unnecessarily reprocessing the complicated data coding process.

Abstract: A recording apparatus and a recording method are provided. Control information is generated by the microcontroller based on the received command. The data preparing unit has a control register and a preparing circuit wherein the control register is used for storing a set of control register values corresponding to the control information, and the preparing circuit is used for generating prepared data based on the set of control register values and storing the prepared data in the data buffer. The recording circuit records on an optical storage media based on the prepared data. The optical storage media has a lead-in area having a plurality of continuous zones. The prepared data includes a plurality of data to be written into the corresponding zones and the plurality of data are stored in the data buffer in the same sequence as the writing sequence to the zones and are read continuously.

Abstract: A pre-pit signal decoder includes a shift register, a pattern comparator, a counting unit, an in-sync signal generating unit and a protection unit. The register receives serial pre-pit bits and converts them into a parallel pre-pit byte. The comparator generates an odd sync bit, an even sync bit, a low bit, and a high bit according to the pre-pit byte and receives a disable signal to operate when the disable signal is not enabled. The counting unit generates a counting value, which marks oddness/evenness of frames of the pre-pit bits and sequence of wobble signals in the frames, according to the odd sync, even sync, low and high bits. The signal generating unit generates an in-sync signal according to the odd sync, even sync, low, and high bits. The protection unit receives the counting value and the in-sync signal to thereby enable the disable signal at positions where the pre-pit bits impossibly exist according to the counting value.

Abstract: The present invention is a method and system for encoding digital data. The encoding system proceeds the step of calculating error detection code and the step of scrambling the main data at the same time to decrease times for the access to the first memory. The present invention comprises a second memory. The encoding system can access more than one recording column per-time, which further decreases times for the access to the first memory.

Abstract: An optical storage disc stores storage information and includes track information. A method for performing a target search on the optical storage disc includes: generating a first intermediate signal according to a readout signal generated by an optical storage device reading the storage information; generating a second intermediate signal according to the track information carried within the readout signal; generating a hybrid address signal according to the first intermediate signal and the second intermediate signal; and performing the target search on the optical storage disc according to the hybrid address signal and a target address set by the optical storage device.

Abstract: The present invention is a method and system for encoding digital data. The encoding system proceeds the step of calculating error detection code and the step of scrambling the main data at the same time to decrease times for the access to the first memory. The present invention comprises a second memory. The encoding system can access more than one recording column per-time, which further decreases times for the access to the first memory.

Abstract: A sampling clock generating device for a burst cutting area (BCA) of an optical disc is disclosed including: a detecting device for detecting a specific pulse period of a BCA reproducing signal reproduced from the BCA; and a clock generator electrically connected to the detecting device for generating a sampling clock according to the detected specific pulse period.

Abstract: An apparatus for writing data to an optical storage media and a servo control unit and a laser diode driver unit thereof. The apparatus making a laser diode emit light includes a servo control unit and a laser diode driver unit. The servo control unit includes a control unit for controlling a burning procedure and a modulation unit for outputting an encoded signal. The laser diode driver unit receives the encoded signal and includes a PLL unit, a write strategy generation unit and a lock/unlock detection unit. The PLL unit outputs at least one of a second clock signal and a second data signal according to the encoded signal. The write strategy generation unit outputs a control signal to control the laser diode according to the second clock signal and the second data signal. The lock/unlock detection unit outputs a lock indicator or an unlock indicator to the control unit.

Abstract: A method for decoding multiword information comprises steps (a) to (h). In step (a), a multiword information cluster including high protective words and low protective words is provided, wherein the multiword information, high protective words and low protective words can be ECC data, BIS data and LDC data, respectively. In step (b), the low protective words are partitioned into multiple groups. In step(c), the low protective words are de-interleaved, so as to generate a low protective word cluster including multiple segments corresponding to the multiple groups. In step (d), any error of the low protective words is detected, so as to generate segment erasure indicators with localities. In step (e), the low protective words and the segment erasure indicators are stored into a first memory, e.g., a DRAM. In step (f), the segment erasure indicators are stored into a second memory, e.g., a SRAM. In step (g), erasure bits of the low protective word are generated based on the segment erasure indicators.

Abstract: A digital sum variation (DSV) computation method and system is proposed, which is capable of determining the DSV value of a bit stream of channel-bit symbols to thereby find the optimal merge-bit symbol for insertion between each succeeding pair of the channel-bit symbols. This DSV computation method and system is characterized in the use of a Zero Digital Sum Variation (ZDSV) principle to determine the DSV. This DSV computation method and system can find the optimal merge-bit symbol for insertion between each succeeding pair of the channel-bit symbols in a more cost-effective manner with the need for a reduced amount of memory and utilizes a lookup table requiring a reduced amount of memory space for storage so that memory space can be reduced as compared to the prior art. This DSV computation method and system is therefore more advantageous to use than the prior art.

Abstract: A path metric computing method applied in a high-speed Viterbi detector and related apparatus thereof are disclosed. The path metric computing apparatus includes a comparator for generating a control signal according a plurality of previous path metrics, a combining circuit for generating a plurality of first output values according to the previous path metrics and branch costs of a plurality of branches of a current state, and a multiplexer, electrically connected to the comparator and the combining circuit, for determining a first path metric of the current state according to the control signal and the output values.

Abstract: A method utilized for detecting a physical mark in a signal read from an optical disc, including: generating a matching signal capable of being utilized to identify the physical mark according to a reference clock and a wobble clock; generating a comparison signal by comparing the matching signal and a wobble data signal; determining whether a period of which the level of the comparison signal surpass a predetermined level within a predetermined period is greater than a threshold or not; and if the period greater than the threshold, generating an indication signal corresponding to the location of the physical mark. Wherein the wobble data signal and the wobble clock is generated according to the read back signal.

Abstract: A method of recording data on an optical storage medium writes different types of data to the same area on the optical storage medium. The data to be written are successively stored in a data buffer in accordance with the sequence of the identification data of a data sector. The same area can be a lead-in area, a data area or a lead-out area. Therefore, a recording circuit can read out the data from the data buffer in accordance with the sequence of corresponding identification data and write them to corresponding tracks on the optical storage medium.

Abstract: The invention provides a decoding circuit and a decoding method for a Viterbi decoder. The decoding circuit of the Viterbi decoder includes a branch metric unit, an add-compare-select unit and a path memory unit. The path memory unit includes a data string controller, a trace write-in register array, an idling register array and a decoding register array. In this invention, a run length limited code is used for effectively solving the problem of generating a complicated trellis diagram after the trellis diagram of the Viterbi decoder is subjected to a longitudinal arrangement. In addition, the register array can perform other operations at different times. Accordingly, a high decoding speed of the Viterbi decoder can be achieved without requiring a lot of registers for data processing.

Abstract: A gain calibration device and method for differential push-pull (DPP) tracking error signals in an optical storage system is provided. The gain calibration method processes the synthesized gain (SPPG) of the sub beam in the DPP tracking error signal components with respect to the main beam. The calibration theorem resides in controlling the objective lens of the pick-up head to form a lens-shift or controlling the tilt of the objective lens relative to the optical disc to make the synthesized DPP tracking error signals generate a correspondingly signal variation owing to the optical path deviation. The synthesized gain is calibrated to make the signal variation a minimum value, and the calibrated synthesized gain is the optimum value.

Abstract: A method for decoding multiword information comprises multiple steps. In step (a), a multiword information cluster, e.g., ECC, including high protective codewords, e.g., BIS, and low protective codewords, e.g., LDC, is provided. In step (b), the high and low protective codewords are stored into a first memory, e.g., DRAM. In step (c), the high protective codewords are decoded to generate high protective word erasure indicators showing whether decoding errors occur. In step (d), the high protective word erasure indicators are stored into a second memory, e.g., SRAM. In step (e), the low protective codewords are decoded. In the meanwhile, an erasure bit for a low protective codeword is marked by finding high protective codewords close to the low protective codeword in the multiword information cluster and looking up the high protective word erasure indicators of the high protective codewords close to the low protective codeword.

Abstract: The present invention discloses an optical disc drive capable of updating firmware, and firmware update method thereof. The disclosed optical disc drive includes a firmware memory, a buffer memory, and a system control chip. The system control chip includes a processor and a memory update controller. When the optical disc drive is under a normal mode, the memory update controller is in an idle state. The processor controls the optical disc drive to fetch an update firmware from an optical disc and store the update firmware into the buffer memory. When the optical disc drive is under a firmware update mode, the processor is in an idle state. The memory update controller fetches the update firmware from the buffer memory and stores the update firmware into the firmware memory without the processor executing an update routine code.

Abstract: The invention discloses a decoding apparatus and the method thereof for decoding a signal retrieved by an optical information reproducing system from an optical information recording medium. N legal codes are predetermined. According to the invention, first, the retrieved signal is converted into a data stream. Then, in a Viterbi decoding manner, the data stream is decoded into a digital code in accordance with a level of the data stream and N reference levels. Then, the binary code is decoded by a binary array into one of the N legal codes, and each of the N legal codes corresponds to one of N reference levels. In particular, the N reference levels are corrected by various detected conditions to enhance the correctness of decoded data.

Abstract: The invention provides a decoding circuit and a decoding method of a Viterbi decoder. The decoding circuit of the Viterbi decoder includes a branch metric unit, an add-compare-select unit and a path memory unit. The path memory unit includes a data string controller, a trace write-in register array, an idling register array and a decoding register array. In this invention, a run length limited code is used for effectively solving the problem of generating a complicated trellis diagram after the trellis diagram of the Viterbi decoder is subjected to a longitudinal arrangement. In addition, the register array can perform other operations at different times. Accordingly, a high decoding speed of the Viterbi decoder can be achieved without requiring a lot of registers for data processing.