Patents by Inventor Wen-Yu Lo

Wen-Yu Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040075964
    Abstract: The present invention relates to a device for protecting high frequency RF integrated circuits from ESD damage. The device comprises at least one varactor-LC circuit tank stacked to avoid the power gain loss by the parasitic capacitance of ESD circuit. The varactor-LC tank could be designed to resonate at the RF operating frequency to avoid the power gain loss from the parasitic capacitance of ESD circuit. Multiple LC-tanks could be stacked for further reduction in the power gain loss. A reverse-biased diode is used as the varactor for both purposes of impedance matching and effective ESD current discharging. Because the inductor is made of metal, both the inductor and the varactor can discharge ESD current when ESD condition happens. It has a high enough ESD level to prevent ESD discharge.
    Type: Application
    Filed: October 21, 2002
    Publication date: April 22, 2004
    Inventors: Ming-Dou Ker, Cheng-Ming Lee, Wen-Yu Lo
  • Patent number: 6671153
    Abstract: A diode string with very low leakage current is used in power supply ESD clamp circuits. By adding an CMOS-Controlled Lateral SCR device into the cascaded diode string, the leakage current of this new diode string with 6 cascaded diodes under 5 Volts (3.3 Volts) forward bias can be controlled below 2.1 (1.07) nA at a temperature of 125° C. in a 0.35 &mgr;m silicide CMOS process. The holding voltage of this design with the CMOS-Controlled Lateral SCR can be linearly adjusted by changing the number of the cascaded diodes in the diode string for the application among the power lines with different voltage levels. The ESD level of this ESD clamp circuit is greater than 8,000 Volts in the Human-Body-Model ESD test. The diodes string is suitable for portable or low-power CMOS Integrated Circuit (IC) devices.
    Type: Grant
    Filed: September 11, 2000
    Date of Patent: December 30, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ming-Dou Ker, Wen-Yu Lo, Hun-Hsien Chang
  • Publication number: 20030235019
    Abstract: An electrostatic discharge (ESD) protection scheme. The scheme utilizes traces in a package substrate to bridge a power ESD clamp circuit and a protected circuit, and comprises a conductive trace in a package substrate and a chip die. The chip die has a protected circuit powered by a first high power rail and a first low power rail, and a power ESD clamp circuit coupled between a second high power rail and a second low power rail. The first high, first low, second high and second low power rails are all fabricated on the IC chip die. The first high power rail is separated from the second high power rail on the chip die, and, during an ESD event, is coupled to the second high power rail through the conductive trace in the package substrate.
    Type: Application
    Filed: June 19, 2002
    Publication date: December 25, 2003
    Inventors: Ming-Dou Ker, Wen-Yu Lo
  • Patent number: 6657835
    Abstract: An ESD protection circuit for Mixed-Voltage I/O by using stacked NMOS transistors with substrate triggering technique is disclosed. The ESD protection circuit contains a set of stacked NMOS transistors with a first NMOS transistor and a second NMOS transistor, a parasitic lateral bipolar transistor, a substrate current generating circuit, and a parasitic substrate resistor. The drain of the first NMOS transistor connects to an I/O pad. The gate of the first NMOS transistor connects to a first working voltage. The source of the first NMOS transistor connects to the drain of the second NMOS transistor. The gate of the second NMOS transistor connects to an internal circuit. The source of the second NMOS transistor connects to a second working voltage. The collector of the parasitic lateral bipolar transistor connects to the drain of the first NMOS transistor and its emitter connects to the source of the second NMOS transistor.
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: December 2, 2003
    Assignee: Silicon Integrated Systems Corp.
    Inventors: Ming-Dou Ker, Chien-Hui Chuang, Wen-Yu Lo
  • Publication number: 20020159208
    Abstract: An ESD protection circuit for Mixed-Voltage I/O by using stacked NMOS transistors with substrate triggering technique is disclosed. The ESD protection circuit contains a set of stacked NMOS transistors with a first NMOS transistor and a second NMOS transistor, a parasitic lateral bipolar transistor, a substrate current generating circuit, and a parasitic substrate resistor. The drain of the first NMOS transistor connects to an I/O pad. The gate of the first NMOS transistor connects to a first working voltage. The source of the first NMOS transistor connects to the drain of the second NMOS transistor. The gate of the second NMOS transistor connects to an internal circuit. The source of the second NMOS transistor connects to a second working voltage. The collector of the parasitic lateral bipolar transistor connects to the drain of the first NMOS transistor and its emitter connects to the source of the second NMOS transistor.
    Type: Application
    Filed: June 7, 2001
    Publication date: October 31, 2002
    Inventors: Ming-Dou Ker, Chien-Hui Chuang, Wen-Yu Lo
  • Publication number: 20020076876
    Abstract: A Method for manufacturing semiconductor devices having ESD protection. The method includes the steps of providing a semiconductor substrate having a well region, forming a gate structure on the semiconductor substrate, the gate structure including an oxide layer, a gate electrode on said oxide layer, and two spacer sidewalls, forming a source region within the well region at one side of the gate structure, forming a drain region within the well region at the other side of the gate structure, forming lightly doped source/drain regions in the well region and beneath the spacer walls of the gate structure wherein the lightly doped source/drain regions have the same conductivity type as the drain region and, and performing an implant with the same conductivity type as the well region as to form an ESD implantation region.
    Type: Application
    Filed: December 15, 2000
    Publication date: June 20, 2002
    Inventors: Ming-Dou Ker, Wen-Yu Lo, Peir-Jy Hu