Patents by Inventor Wen-Yu Tseng
Wen-Yu Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11943877Abstract: A circuit board structure includes a circuit substrate having opposing first and second sides, a redistribution structure disposed at the first side, and a dielectric structure disposed at the second side. The circuit substrate includes a first circuit layer disposed at the first side and a second circuit layer disposed at the second side. The redistribution structure is electrically coupled to the circuit substrate and includes a first leveling dielectric layer covering the first circuit layer, a first thin-film dielectric layer disposed on the first leveling dielectric layer and having a material different from the first leveling dielectric layer, and a first redistributive layer disposed on the first thin-film dielectric layer and penetrating through the first thin-film dielectric layer and the first leveling dielectric layer to be in contact with the first circuit layer. The dielectric structure includes a second leveling dielectric layer disposed below the second circuit layer.Type: GrantFiled: March 2, 2022Date of Patent: March 26, 2024Assignee: Unimicron Technology Corp.Inventors: Wen-Yu Lin, Kai-Ming Yang, Chen-Hao Lin, Pu-Ju Lin, Cheng-Ta Ko, Chin-Sheng Wang, Guang-Hwa Ma, Tzyy-Jang Tseng
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Publication number: 20240088182Abstract: In some embodiments, an image sensor is provided. The image sensor includes a photodetector disposed in a semiconductor substrate. A wave guide filter having a substantially planar upper surface is disposed over the photodetector. The wave guide filter includes a light filter disposed in a light filter grid structure. The light filter includes a first material that is translucent and has a first refractive index. The light filter grid structure includes a second material that is translucent and has a second refractive index less than the first refractive index.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Chien Yu, Ting-Cheng Chang, Wen-Hau Wu, Chih-Kung Chang
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Patent number: 11308016Abstract: A USB integrated circuit includes three TX connecting component pairs and three RX connecting component pairs. The first TX connecting component pair and the first RX connecting component pair are respectively coupled to the first TX pin pair and the first RX pin pair of the first USB connector. The second TX connecting component pair and the second RX connecting component pair are respectively coupled to the first TX pin pair and the first RX pin pair of a second USB connector. The third TX connecting component pair is coupled to the second TX pin pair of the first USB connector or to the second TX pin pair of the second USB connector. The third RX connecting component pair is coupled to the second RX pin pair of the first USB connector or to the second RX pin pair of the second USB connector.Type: GrantFiled: October 24, 2019Date of Patent: April 19, 2022Assignee: VIA LABS, INC.Inventors: Wen-Yu Tseng, Wen-Hao Cheng, Terrance Shiyang Shih
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Publication number: 20210064558Abstract: A USB integrated circuit includes three TX connecting component pairs and three RX connecting component pairs. The first TX connecting component pair and the first RX connecting component pair are respectively coupled to the first TX pin pair and the first RX pin pair of the first USB connector. The second TX connecting component pair and the second RX connecting component pair are respectively coupled to the first TX pin pair and the first RX pin pair of a second USB connector. The third TX connecting component pair is coupled to the second TX pin pair of the first USB connector or to the second TX pin pair of the second USB connector. The third RX connecting component pair is coupled to the second RX pin pair of the first USB connector or to the second RX pin pair of the second USB connector.Type: ApplicationFiled: October 24, 2019Publication date: March 4, 2021Applicant: VIA LABS, INC.Inventors: Wen-Yu Tseng, Wen-Hao Cheng, Terrance Shiyang Shih
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Patent number: 9158329Abstract: A clock generator is provided. The clock generator includes a crystal oscillator, an inverter coupled to the crystal oscillator in parallel, a first circuit and a second circuit. The crystal oscillator has a first terminal and a second terminal. The inverter generates a first signal and a second signal at the first and second terminals of the crystal oscillator, respectively. The first circuit coupled to the first terminal of the crystal oscillator generates a first clock signal with a constant frequency according to the first signal. The second circuit coupled to the second terminal of the crystal oscillator generates a second clock signal with a variable frequency according to the second signal.Type: GrantFiled: July 5, 2013Date of Patent: October 13, 2015Assignee: VIA TECHNOLOGIES, INC.Inventors: Wen-Yu Tseng, Hsiao-Chyi Lin
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Patent number: 8706924Abstract: A data link transmitter in a PCI Express device for managing PCI-Express TLPs and DLLPs. The data link transmitter includes a priority system in which a DLLP for initializing flow control has highest priority, and an idle data character has lowest priority. Various embodiments include: a DLLP for power state entrance is lower priority than the DLLP for initializing flow control; a replay TLP for retry buffer re-transmission is lower priority than the DLLP for power state entrance, and a new TLP is lower priority than the replay TLP; an Ack/Nak DLLP is lower priority than the new TLP, a DLLP for updating flow control is lower priority than the Ack/Nak TLP, and a DLLP for acknowledging the DLLP for power state entrance is lower priority than the DLLP for updating flow control; a DLLP for updating flow control is lower priority than the DLLP for power state entrance.Type: GrantFiled: July 24, 2009Date of Patent: April 22, 2014Assignee: Via Technologies, Inc.Inventors: Yen-Ting Lai, Wen-Yu Tseng
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Publication number: 20130304961Abstract: A HUB control chip implemented in a specific package is provided. The HUB control chip includes a plurality of transmission modules and a plurality of pins. The plurality of the pins include: a plurality of data pin groups coupled to one of the plurality of transmission modules respectively. Each of the plurality of data pin groups includes: a first sub-group, receiving and transmitting a first pair of differential signals conforming to the USB 2.0 standard; a second sub-group, receiving a second pair of differential signals conforming to the USB 3.0 standard; and a third sub-group, transmitting a third pair of differential signals conforming to the USB 3.0 standard. The number of the plurality of the pins is less than or equal to 52.Type: ApplicationFiled: May 8, 2013Publication date: November 14, 2013Applicant: VIA TECHNOLOGIES, INC.Inventors: Hsiao-Chyi LIN, Wen-Yu TSENG
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Publication number: 20130297962Abstract: A clock generator is provided. The clock generator includes a crystal oscillator, an inverter coupled to the crystal oscillator in parallel, a first circuit and a second circuit. The crystal oscillator has a first terminal and a second terminal The inverter generates a first signal and a second signal at the first and second terminals of the crystal oscillator, respectively. The first circuit coupled to the first terminal of the crystal oscillator generates a first clock signal with a constant frequency according to the first signal. The second circuit coupled to the second terminal of the crystal oscillator generates a second clock signal with a variable frequency according to the second signal.Type: ApplicationFiled: July 5, 2013Publication date: November 7, 2013Inventors: Wen-Yu TSENG, Hsiao-Chyi LIN
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Patent number: 8554977Abstract: An integrated circuit for accessing a universal serial bus (USB) device via a USB 3.0 receptacle is provided. The integrated circuit includes a plurality of pins and a controlling unit. The pins include a first group for coupling to a first pair of differential pins of the USB receptacle, a second group for coupling to a second pair of differential pins of the USB receptacle, a third group for coupling to a third pair of differential pins to the USB receptacle, a ground pin, a first and second power pins. The second group is disposed between the first and third groups. The controlling unit controls the plurality of pins to receive or transmit the USB 2.0 or USB 3.0 signals.Type: GrantFiled: November 1, 2012Date of Patent: October 8, 2013Assignee: Via Technologies, Inc.Inventor: Wen-Yu Tseng
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Patent number: 8499186Abstract: A clock generator is provided. The clock generator includes a crystal oscillator, an inverter coupled to the crystal oscillator in parallel, a first circuit and a second circuit. The crystal oscillator has a first terminal and a second terminal. The inverter generates a first signal and a second signal at the first and second terminals of the crystal oscillator, respectively. The first circuit coupled to the first terminal of the crystal oscillator generates a first clock signal with a constant frequency according to the first signal. The second circuit coupled to the second terminal of the crystal oscillator generates a second clock signal with a variable frequency according to the second signal.Type: GrantFiled: May 10, 2010Date of Patent: July 30, 2013Assignee: Via Technologies, Inc.Inventors: Wen-Yu Tseng, Hsiao-Chyi Lin
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Patent number: 8347017Abstract: An integrated circuit for accessing a universal serial bus (USB) device via a USB 3.0 receptacle is provided. The integrated circuit includes a plurality of pins and a controlling unit. The pins include a first group for receiving and transmitting a first pair of differential signals of the USB device, a second group for receiving a second pair of differential signals from the USB device, and a third group for transmitting a third pair of differential signals to the USB device. The second group is disposed between the first and third groups. The controlling unit controls the plurality of pins to receive or transmit the first, second or third pair of differential signals.Type: GrantFiled: May 21, 2009Date of Patent: January 1, 2013Assignee: Via Technologies, Inc.Inventor: Wen-Yu Tseng
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Patent number: 8006014Abstract: A PCI-Express data link transmitter includes a plurality of arbiters, each employing a distinct priority rule to select one of multiple scheduled TLPs and DLLPs based on their distinct types. A selector selects one of the arbiters to select the one of the multiple scheduled TLPs and DLLPs for transmission. A programmable storage element provides a value to control the selector. In one embodiment, the distinct priority rule employed by at least a first of the arbiters prioritizes TLPs higher than Ack/Nak DLLPs, and the distinct priority rule employed by at least a second of the arbiters prioritizes Ack/Nak DLLPs higher than TLPs. In one embodiment, at least a first arbiter prioritizes TLPs higher than Ack/Nak DLLPs and UpdateFC DLLPs, at least a second arbiter prioritizes Ack/Nak DLLPs higher than TLPs and UpdateFC DLLPs, and at least a third arbiter prioritizes UpdateFC DLLPs higher than TLPs and Ack/Nak DLLPs.Type: GrantFiled: July 24, 2009Date of Patent: August 23, 2011Assignee: VIA Technologies, Inc.Inventors: Yen-Ting Lai, Wen-Yu Tseng
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Publication number: 20110138214Abstract: A clock generator is provided. The clock generator includes a crystal oscillator, an inverter coupled to the crystal oscillator in parallel, a first circuit and a second circuit. The crystal oscillator has a first terminal and a second terminal. The inverter generates a first signal and a second signal at the first and second terminals of the crystal oscillator, respectively. The first circuit coupled to the first terminal of the crystal oscillator generates a first clock signal with a constant frequency according to the first signal. The second circuit coupled to the second terminal of the crystal oscillator generates a second clock signal with a variable frequency according to the second signal.Type: ApplicationFiled: May 10, 2010Publication date: June 9, 2011Applicant: VIA TECHNOLOGIES, INC.Inventors: Wen-Yu Tseng, Hsiao-Chyi Lin
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Patent number: 7869491Abstract: A data transceiver and method thereof are disclosed. The data transceiver generates a gated control signal according to a valid signal and a clock signal. The packets are outputted according to the gated control signal.Type: GrantFiled: May 11, 2007Date of Patent: January 11, 2011Assignee: VIA Technologies, Inc.Inventors: Iuan-Tsung Jeng, Wen-Yu Tseng
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Patent number: 7849340Abstract: A peripheral component interconnect express (PCIE) data transmission system and link state managing method thereof are disclosed. The PCIE data transmission system includes an upstream device, a downstream device and a link. When the link is in a first link state, the downstream device and the upstream device transmit data normally via the link. When the upstream device outputs a turn-off signal to the downstream device, a time period is counted. The downstream device outputs an acknowledging signal to response the turn-off signal. If the upstream device does not receive the acknowledging signal within the time period, the link is transited from the first link state to second link state to remove the power of the link.Type: GrantFiled: May 9, 2006Date of Patent: December 7, 2010Assignee: Via Technologies, Inc.Inventors: Wen-Yu Tseng, Jin-Liang Mao
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Publication number: 20100233908Abstract: An integrated circuit for accessing a universal serial bus (USB) device via a USB 3.0 receptacle is provided. The integrated circuit includes a plurality of pins and a controlling unit. The pins include a first group for receiving and transmitting a first pair of differential signals of the USB device, a second group for receiving a second pair of differential signals from the USB device, and a third group for transmitting a third pair of differential signals to the USB device. The second group is disposed between the first and third groups. The controlling unit controls the plurality of pins to receive or transmit the first, second or third pair of differential signals.Type: ApplicationFiled: May 21, 2009Publication date: September 16, 2010Applicant: VIA TECHNOLOGIES, INC.Inventor: Wen-Yu Tseng
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Patent number: 7721031Abstract: A PCI Express link state management system and method thereof is disclosed. The PCI Express link state management system includes an upstream device, a downstream device and a link. The upstream device outputs a configuration request to the downstream device to change a device power state of the downstream device. At the time, the link is in a first link state. The downstream device outputs a power entering signal to the upstream device and counts a time period. The link enters to a recovery state and further then return to the first link state if the downstream device does not receive a power request acknowledging signal before the time period is expired.Type: GrantFiled: May 12, 2006Date of Patent: May 18, 2010Assignee: VIA Technologies, Inc.Inventors: Wen-Yu Tseng, Yuan-Zong Cheng
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Publication number: 20100115311Abstract: A PCI Express system and a method of transitioning link state thereof. The PCI Express system includes an upstream component, a downstream component and a link. The upstream component and the downstream component transmit data to each other via the link.Type: ApplicationFiled: January 11, 2010Publication date: May 6, 2010Inventors: Wen-Yu Tseng, Wei-Lin Wang
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Publication number: 20100042766Abstract: A PCI-Express data link transmitter includes a plurality of arbiters, each employing a distinct priority rule to select one of multiple scheduled TLPs and DLLPs based on their distinct types. A selector selects one of the arbiters to select the one of the multiple scheduled TLPs and DLLPs for transmission. A programmable storage element provides a value to control the selector. In one embodiment, the distinct priority rule employed by at least a first of the arbiters prioritizes TLPs higher than Ack/Nak DLLPs, and the distinct priority rule employed by at least a second of the arbiters prioritizes Ack/Nak DLLPs higher than TLPs. In one embodiment, at least a first arbiter prioritizes TLPs higher than Ack/Nak DLLPs and UpdateFC DLLPs, at least a second arbiter prioritizes Ack/Nak DLLPs higher than TLPs and UpdateFC DLLPs, and at least a third arbiter prioritizes UpdateFC DLLPs higher than TLPs and Ack/Nak DLLPs.Type: ApplicationFiled: July 24, 2009Publication date: February 18, 2010Applicant: VIA TECHNOLOGIES, INC.Inventors: Yen-Ting Lai, Wen-Yu Tseng
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Publication number: 20100040087Abstract: A data link transmitter in a PCI Express device for managing PCI-Express TLPs and DLLPs. The data link transmitter includes a priority system in which a DLLP for initializing flow control has highest priority, and an idle data character has lowest priority. Various embodiments include: a DLLP for power state entrance is lower priority than the DLLP for initializing flow control; a replay TLP for retry buffer re-transmission is lower priority than the DLLP for power state entrance, and a new TLP is lower priority than the replay TLP; an Ack/Nak DLLP is lower priority than the new TLP, a DLLP for updating flow control is lower priority than the Ack/Nak TLP, and a DLLP for acknowledging the DLLP for power state entrance is lower priority than the DLLP for updating flow control; a DLLP for updating flow control is lower priority than the DLLP for power state entrance.Type: ApplicationFiled: July 24, 2009Publication date: February 18, 2010Applicant: VIA TECHNOLOGIES, INC.Inventors: Yen-Ting Lai, Wen-Yu Tseng