Patents by Inventor Wen-Yueh Jang
Wen-Yueh Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11257830Abstract: In the memory structure, a pair of gate stack structures is on a first dielectric layer and separated from each other. Each of the gate stack structures includes a word line and a second dielectric layer. A third dielectric layer is on the sidewall of the gate stack structures. A pair of floating gates is between the gate stack structures. Each of the floating gates is on the third dielectric layer on the sidewall of the corresponding gate stack structure. The top surface of the floating gates is not higher than the that of the second dielectric layer. A fourth dielectric layer covers the first and third dielectric layers, and the floating gates. A control gate is on the fourth dielectric layer between the floating gates. A doped region is in the substrate beside the gate stack structures. An erase gate is above the control gate and the floating gates.Type: GrantFiled: December 9, 2020Date of Patent: February 22, 2022Assignee: Powerchip Semiconductor Manufacturing CorporationInventor: Wen-Yueh Jang
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Publication number: 20210091099Abstract: In the memory structure, a pair of gate stack structures is on a first dielectric layer and separated from each other. Each of the gate stack structures includes a word line and a second dielectric layer. A third dielectric layer is on the sidewall of the gate stack structures. A pair of floating gates is between the gate stack structures. Each of the floating gates is on the third dielectric layer on the sidewall of the corresponding gate stack structure. The top surface of the floating gates is not higher than the that of the second dielectric layer. A fourth dielectric layer covers the first and third dielectric layers, and the floating gates. A control gate is on the fourth dielectric layer between the floating gates. A doped region is in the substrate beside the gate stack structures. An erase gate is above the control gate and the floating gates.Type: ApplicationFiled: December 9, 2020Publication date: March 25, 2021Applicant: Powerchip Semiconductor Manufacturing CorporationInventor: Wen-Yueh Jang
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Patent number: 10896910Abstract: A memory structure and a manufacturing method thereof are provided. In the memory structure, a first dielectric layer is disposed on a substrate; a pair of gate stack structures is disposed on the first dielectric layer and each gate stack structure includes a word line, an erase gate and a second dielectric layer; a third dielectric layer is disposed on the surfaces of the gate stack structures; a pair of floating gates is disposed between the gate stack structures and located respectively on sidewalls of the gate stack structures, and top surfaces of the floating gates are lower than those of the erase gates; a fourth dielectric layer covers the first and third dielectric layers and the floating gates; a control gate is disposed on the fourth dielectric layer between the floating gates; and a doped region is disposed in the substrate beside the gate stack structures.Type: GrantFiled: March 26, 2019Date of Patent: January 19, 2021Assignee: Powerchip Semiconductor Manufacturing CorporationInventor: Wen-Yueh Jang
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Patent number: 10868196Abstract: A memory device and a manufacturing method are provided. The memory device includes a substrate, first and second word lines, first and second charge trapping layers, a first drain region and a first source region. The substrate has first and second recesses extending along a first direction. The first and second word lines are respectively disposed in the first and second recesses. The first and second charge trapping layers are respectively disposed in the first and second recesses. The first charge trapping layer is located between the first word line and a sidewall of the first recess. The second charge trapping layer is located between the second word line and a sidewall of the second recess. The first and second drain regions are disposed in the substrate, and respectively extending between the first and the second charge trapping layers along a second direction.Type: GrantFiled: March 25, 2019Date of Patent: December 15, 2020Assignee: Powerchip Semiconductor Manufacturing CorporationInventor: Wen-Yueh Jang
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Publication number: 20200251480Abstract: A memory structure and a manufacturing method thereof are provided. In the memory structure, a first dielectric layer is disposed on a substrate; a pair of gate stack structures is disposed on the first dielectric layer and each gate stack structure includes a word line, an erase gate and a second dielectric layer; a third dielectric layer is disposed on the surfaces of the gate stack structures; a pair of floating gates is disposed between the gate stack structures and located respectively on sidewalls of the gate stack structures, and top surfaces of the floating gates are lower than those of the erase gates; a fourth dielectric layer covers the first and third dielectric layers and the floating gates; a control gate is disposed on the fourth dielectric layer between the floating gates; and a doped region is disposed in the substrate beside the gate stack structures.Type: ApplicationFiled: March 26, 2019Publication date: August 6, 2020Applicant: Powerchip Technology CorporationInventor: Wen-Yueh Jang
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Publication number: 20200194598Abstract: A memory device and a manufacturing method are provided. The memory device includes a substrate, first and second word lines, first and second charge trapping layers, a first drain region and a first source region. The substrate has first and second recesses extending along a first direction. The first and second word lines are respectively disposed in the first and second recesses. The first and second charge trapping layers are respectively disposed in the first and second recesses. The first charge trapping layer is located between the first word line and a sidewall of the first recess. The second charge trapping layer is located between the second word line and a sidewall of the second recess. The first and second drain regions are disposed in the substrate, and respectively extending between the first and the second charge trapping layers along a second direction.Type: ApplicationFiled: March 25, 2019Publication date: June 18, 2020Applicant: Powerchip Technology CorporationInventor: Wen-Yueh Jang
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Patent number: 9966530Abstract: A resistive random access memory device and a method for fabricating the same are presented. The resistive random access memory device includes a first electrode having a first dopant within. A second electrode is disposed on the first electrode. A resistive switching layer is disposed between the first electrode and the second electrode.Type: GrantFiled: June 27, 2017Date of Patent: May 8, 2018Assignee: WINBOND ELECTRONICS CORP.Inventors: Wen-Yueh Jang, Chia Hua Ho
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Publication number: 20170294579Abstract: A resistive random access memory device and a method for fabricating the same are presented. The resistive random access memory device includes a first electrode having a first dopant within. A second electrode is disposed on the first electrode. A resistive switching layer is disposed between the first electrode and the second electrode.Type: ApplicationFiled: June 27, 2017Publication date: October 12, 2017Inventors: Wen-Yueh JANG, Chia Hua HO
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Patent number: 9728720Abstract: A resistive random access memory device and a method for fabricating the same are presented. The resistive random access memory device includes a first electrode having a first dopant within. A second electrode is disposed on the first electrode. A resistive switching layer is disposed between the first electrode and the second electrode.Type: GrantFiled: September 22, 2015Date of Patent: August 8, 2017Assignee: WINBOND ELECTRONICS CORP.Inventors: Wen-Yueh Jang, Chia Hua Ho
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Publication number: 20160087199Abstract: A resistive random access memory device and a method for fabricating the same are presented. The resistive random access memory device includes a first electrode having a first dopant within. A second electrode is disposed on the first electrode. A resistive switching layer is disposed between the first electrode and the second electrode.Type: ApplicationFiled: September 22, 2015Publication date: March 24, 2016Inventors: Wen-Yueh JANG, Chia Hua HO
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Patent number: 9203020Abstract: Provided is a resistance memory device including a dielectric layer, a conductive layer, a bottom electrode, a top electrode and a variable resistance layer. The dielectric layer is disposed on a substrate and has a first opening constituted by a lower opening and an upper opening. The conductive layer fills up the lower opening. The bottom electrode is disposed on the bottom and on at least a portion of the sidewall of the upper opening. The top electrode is disposed in the upper opening. The variable resistance layer is disposed between the top electrode and the bottom electrode.Type: GrantFiled: February 26, 2015Date of Patent: December 1, 2015Assignee: Winbond Electronics Corp.Inventors: Wen-Yueh Jang, Ming-Chung Chiang
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Patent number: 9076797Abstract: A 3-D memory is provided. Each word line layer has word lines and gaps alternately arranged along a first direction. Gaps include first group and second group of gaps alternately arranged. A first bit line layer is on word line layers and has first bit lines along a second direction. A first conductive pillar array through word line layers connects the first bit line layer and includes first conductive pillars in first group of gaps. A first memory element is between a first conductive pillar and an adjacent word line. A second bit line layer is below word line layers and has second bit lines along the second direction. A second conductive pillar array through word line layers connects the second bit line layer and includes second conductive pillars in second group of gaps. A second memory element is between a second conductive pillar and an adjacent word line.Type: GrantFiled: June 27, 2014Date of Patent: July 7, 2015Assignee: Winbond Electronics Corp.Inventor: Wen-Yueh Jang
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Publication number: 20150171322Abstract: Provided is a resistance memory device including a dielectric layer, a conductive layer, a bottom electrode, a top electrode and a variable resistance layer. The dielectric layer is disposed on a substrate and has a first opening constituted by a lower opening and an upper opening. The conductive layer fills up the lower opening. The bottom electrode is disposed on the bottom and on at least a portion of the sidewall of the upper opening. The top electrode is disposed in the upper opening. The variable resistance layer is disposed between the top electrode and the bottom electrode.Type: ApplicationFiled: February 26, 2015Publication date: June 18, 2015Inventors: Wen-Yueh Jang, Ming-Chung Chiang
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Patent number: 9012880Abstract: Provided is a resistance memory device including a dielectric layer, a conductive layer, a bottom electrode, a top electrode and a variable resistance layer. The dielectric layer is disposed on a substrate and has a first opening constituted by a lower opening and an upper opening. The conductive layer fills up the lower opening. The bottom electrode is disposed on the bottom and on at least a portion of the sidewall of the upper opening. The top electrode is disposed in the upper opening. The variable resistance layer is disposed between the top electrode and the bottom electrode.Type: GrantFiled: February 21, 2013Date of Patent: April 21, 2015Assignee: Winbond Electronics Corp.Inventors: Wen-Yueh Jang, Ming-Chung Chiang
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Patent number: 8999781Abstract: A method for fabricating a semiconductor device is described. A plurality of isolation structures is formed in a substrate. The isolation structures are arranged in parallel and extend along a first direction. A well of a first conductive type is formed in the substrate. A plurality of first doped regions of a second conductive type is formed in the well. Each of the first doped regions is formed between two adjacent isolation structures. A plurality of gates of the second conductive type is formed on the substrate. The gates are arranged in parallel and extend along a second direction different from the first direction. One of the first doped regions is connected to one of the gates. A plurality of second doped regions of the first conductive type is formed in the well. Each of the second doped regions is formed in the first doped regions between two adjacent gates.Type: GrantFiled: March 18, 2013Date of Patent: April 7, 2015Assignee: Winbond Electronics Corp.Inventor: Wen-Yueh Jang
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Publication number: 20140306353Abstract: A 3-D memory is provided. Each word line layer has word lines and gaps alternately arranged along a first direction. Gaps include first group and second group of gaps alternately arranged. A first bit line layer is on word line layers and has first bit lines along a second direction. A first conductive pillar array through word line layers connects the first bit line layer and includes first conductive pillars in first group of gaps. A first memory element is between a first conductive pillar and an adjacent word line. A second bit line layer is below word line layers and has second bit lines along the second direction. A second conductive pillar array through word line layers connects the second bit line layer and includes second conductive pillars in second group of gaps. A second memory element is between a second conductive pillar and an adjacent word line.Type: ApplicationFiled: June 27, 2014Publication date: October 16, 2014Inventor: Wen-Yueh Jang
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Patent number: 8835990Abstract: A 3-D memory is provided. Each word line layer has word lines and gaps alternately arranged along a first direction. Gaps include first group and second group of gaps alternately arranged. A first bit line layer is on word line layers and has first bit lines along a second direction. A first conductive pillar array through word line layers connects the first bit line layer and includes first conductive pillars in first group of gaps. A first memory element is between a first conductive pillar and an adjacent word line. A second bit line layer is below word line layers and has second bit lines along the second direction. A second conductive pillar array through word line layers connects the second bit line layer and includes second conductive pillars in second group of gaps. A second memory element is between a second conductive pillar and an adjacent word line.Type: GrantFiled: August 12, 2011Date of Patent: September 16, 2014Assignee: Winbond Electronics Corp.Inventor: Wen-Yueh Jang
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Publication number: 20140231742Abstract: Provided is a resistance memory device including a dielectric layer, a conductive layer, a bottom electrode, a top electrode and a variable resistance layer. The dielectric layer is disposed on a substrate and has a first opening constituted by a lower opening and an upper opening. The conductive layer fills up the lower opening. The bottom electrode is disposed on the bottom and on at least a portion of the sidewall of the upper opening. The top electrode is disposed in the upper opening. The variable resistance layer is disposed between the top electrode and the bottom electrode.Type: ApplicationFiled: February 21, 2013Publication date: August 21, 2014Applicant: WINBOND ELECTRONICS CORP.Inventors: Wen-Yueh Jang, Ming-Chung Chiang
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Patent number: 8421127Abstract: A semiconductor device and a method for fabricating the same are described. The semiconductor device includes a well of a first conductive type, first doped regions of a second conductive type, gates of the second conductive type, second doped regions of the first conductive type, and isolation structures. The well is disposed in a substrate. The first doped regions are disposed in the well. The first doped regions are arranged in parallel and extend along a first direction. The gates are disposed on the substrate. The gates are arranged in parallel and extend along a second direction different from the first direction. One of the first doped regions is electrically connected to one of the gates. Each of the second doped regions is disposed in the first doped regions between two adjacent gates. Each of the isolation structures is disposed in the substrate between two adjacent first doped regions.Type: GrantFiled: July 15, 2011Date of Patent: April 16, 2013Assignee: Windbond Electronics Corp.Inventor: Wen-Yueh Jang
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Publication number: 20130037860Abstract: A 3-D memory is provided. Each word line layer has word lines and gaps alternately arranged along a first direction. Gaps include first group and second group of gaps alternately arranged. A first bit line layer is on word line layers and has first bit lines along a second direction. A first conductive pillar array through word line layers connects the first bit line layer and includes first conductive pillars in first group of gaps. A first memory element is between a first conductive pillar and an adjacent word line. A second bit line layer is below word line layers and has second bit lines along the second direction. A second conductive pillar array through word line layers connects the second bit line layer and includes second conductive pillars in second group of gaps. A second memory element is between a second conductive pillar and an adjacent word line.Type: ApplicationFiled: August 12, 2011Publication date: February 14, 2013Applicant: WINBOND ELECTRONICS CORP.Inventor: Wen-Yueh Jang