Abstract: The present invention discloses a method for manufacturing a flash memory cell having a horizontal surrounding gate (HSG). The flash memory cell of the present invention is formed on a trench of an isolation region, and a channel of the flash memory cell composed of a semiconductor film is encompassed and surrounded by a tunneling oxide layer, a floating gate, a dielectric layer, and a control gate in sequence. In addition, the floating gate and the control gate are also formed on the trench below the channel. Therefore, the leakage current of the channel can be reduced, and the short channel effect can be avoided. Furthermore, the coupling capacitor between the control gate and the floating gate is increased without increasing the cell size. Besides, the data can be programmed and erased by a Fowler-Nordheim (FN) tunneling effect.

Abstract: A method of manufacturing an MOSFET. A substrate is provided. A trench is formed in the substrate. A sacrificial layer is formed to fill the trench. A doped semiconductive layer is formed over the substrate. The doped semiconductive layer is patterned to form a device region, wherein the device region spans the sacrificial layer to expose a portion of the sacrificial layer. The sacrificial layer is removed. A gate dielectric layer is formed on the surface of the trench and on the top surface and the bottom surface of the device region. A conductive layer is formed on the gate dielectric layer. The conductive layer is patterned to form a horizontal surround gate surrounding the device region. A source/drain region is formed in a portion of the substrate adjacent to the device region.

Abstract: A method of manufacturing an MOSFET. A substrate is provided. A trench filled with an insulating layer is formed in the substrate. The upper portion of the insulating layer is removed and then a spacer is formed on the side-wall of the trench. A sacrificial layer is formed to fill the trench. A doped semiconductive layer is formed over the substrate and then patterned to form a device region, wherein the device region spans the sacrificial layer to expose a portion of the sacrificial layer. The sacrificial layer is removed. A gate dielectric layer is formed on the exposed surface of the device region. A conductive layer is formed on the gate dielectric layer and then patterned to form a horizontal surround gate surrounding the device region. A source/drain region is formed in a portion of the substrate adjacent to the device region.

Abstract: The present invention describes a method for fabricating flash memory. In accordance with the present invention, the forming of the floating gate does not require an additional photolithography step. As a result, the misalignment problem between the floating gate and the active area may be resolved. On the other hand, because of the specific floating gate structure of the present invention, high coupling capacitance between the floating gate and control gate can be achieved by recessing the shallow trench isolation more. Therefore, the method does not sacrifice the whole cell size.

Abstract: The present invention discloses a structure of a horizontal surrounding gate (HSG) flash memory cell and a method for manufacturing the same. The HSG flash memory cell of the present invention is located on a trench of an isolation region, and a channel region of the HSG flash memory cell composed of a semiconductor film is encompassed by a tunneling oxide layer, a floating gate, and a control gate in sequence. The floating gate and the control gate are also formed on the trench below the channel region. Therefore, the leakage current of the channel can be improved, and the short channel effect cannot be induced by junction depth of a source/drain. Furthermore, the coupling capacitor between the control gate and the floating gate is increased easily by increasing the depth of the trench.

Abstract: The present invention describes a method for fabricating flash memory. In accordance with the present invention, the forming of the floating gate does not require an additional photolithography step. As a result, the misalignment problem between the floating gate and the active area may be resolved. On the other hand, because of the specific floating gate structure of the present invention, high coupling capacitance between the floating gate and control gate can be achieved by recessing the shallow trench isolation more. Therefore, the method does not sacrifice the whole cell size.

Abstract: A structure and a manufacture method of a DRAM device with deep trench capacitors are described. Each capacitor has a collar oxide layer with different height for electrical isolation and leakage reduction. Further, the DRAM device has strip-type active areas to improve some optical errors and thus reduce sufficiently the contact resistance of a buried strap film of a capacitor.

Abstract: The present invention discloses a structure of a flash memory cell having a horizontal surrounding gate (HSG) and a method for manufacturing the same. The flash memory cell of the present invention is formed on a trench of an isolation region, and a channel of the flash memory cell composed of a semiconductor film is encompassed and surrounded by a tunneling oxide layer, a floating gate, a dielectric layer, and a control gate in sequence. In addition, the floating gate and the control gate are also formed on the trench below the channel. Therefore, the leakage current of the channel can be reduced, and the short channel effect can be avoided. Furthermore, the coupling capacitor between the control gate and the floating gate is increased without increasing the cell size. Besides, the data can be programmed and erased by a Fowler-Nordheim (FN) tunneling effect.

Abstract: The present invention discloses a structure of a horizontal surrounding gate (HSG) flash memory cell. The HSG flash memory cell of the present invention is located on a trench of an isolation region, and a channel region of the HSG flash memory cell composed of a semiconductor film is encompassed by a tunneling oxide layer, a floating gate, and a control gate in sequence. The floating gate and the control gate are also formed on the trench below the channel region. Therefore, the leakage current of the channel can be improved, and the short channel effect cannot be induced by junction depth of a source/drain. Furthermore, the coupling capacitor between the control gate and the floating gate is increased easily by increasing the depth of the trench.

Abstract: The present invention discloses a structure of a horizontal surrounding gate (HSG) flash memory cell and a method for manufacturing the same. The HSG flash memory cell of the present invention is located on a trench of an isolation region, and a channel region of the HSG flash memory cell composed of a semiconductor film is encompassed by a tunneling oxide layer, a floating gate, and a control gate in sequence. The floating gate and the control gate are also formed on the trench below the channel region. Therefore, the leakage current of the channel can be improved, and the short channel effect cannot be induced by junction depth of a source/drain. Furthermore, the coupling capacitor between the control gate and the floating gate is increased easily by increasing the depth of the trench.

Abstract: A method of manufacturing an MOSFET. A substrate is provided. A trench is formed in the substrate. A sacrificial layer is formed to fill the trench. A doped semiconductive layer is formed over the substrate. The doped semiconductive layer is patterned to form a device region, wherein the device region spans the sacrificial layer to expose a portion of the sacrificial layer. The sacrificial layer is removed. A gate dielectric layer is formed on the surface of the trench and on the top surface and the bottom surface of the device region. A conductive layer is formed on the gate dielectric layer. The conductive layer is patterned to form a horizontal surround gate surrounding the device region. A source/drain region is formed in a portion of the substrate adjacent to the device region.

Abstract: The present invention discloses a structure of a flash memory cell having a horizontal surrounding gate (HSG) and a method for manufacturing the same. The flash memory cell of the present invention is formed on a trench of an isolation region, and a channel of the flash memory cell composed of a semiconductor film is encompassed and surrounded by a tunneling oxide layer, a floating gate, a dielectric layer, and a control gate in sequence. In addition, the floating gate and the control gate are also formed on the trench below the channel. Therefore, the leakage current of the channel can be reduced, and the short channel effect can be avoided. Furthermore, the coupling capacitor between the control gate and the floating gate is increased without increasing the cell size. Besides, the data can be programmed and erased by a Fowler-Nordheim (FN) tunneling effect.

Abstract: A method of manufacturing an MOSFET. A substrate is provided. A trench filled with an insulating layer is formed in the substrate. The upper portion of the insulating layer is removed and then a spacer is formed on the side-wall of the trench. A sacrificial layer is formed to fill the trench. A doped semiconductive layer is formed over the substrate and then patterned to form a device region, wherein the device region spans the sacrificial layer to expose a portion of the sacrificial layer. The sacrificial layer is removed. A gate dielectric layer is formed on the exposed surface of the device region. A conductive layer is formed on the gate dielectric layer and then patterned to form a horizontal surround gate surrounding the device region. A source/drain region is formed in a portion of the substrate adjacent to the device region.

Abstract: A method for forming an array of DRAM cells with buried trench capacitors is provided. The present method utilizes a photolithography and etching process to laterally remove away the parts of a collar oxide layer around the inner sidewalls of buried trench capacitors neighboring with each other in a pair of neighboring buried trench capacitors before a dielectric layer of the capacitor is formed. By way of replacing the removed parts of the collar oxide layer with a silicon nitride/silicon dioxide (NO) composite layer and using a strip type pattern along the pattern of the buried trench capacitors to define active areas for source/drain regions of access transistors over the buried trench capacitors, additional capacitance is occurred in the peripheral area of the neighboring buried trench capacitors which are not used by a conventional buried trench capacitor.

Abstract: A process for forming a self-aligned BJT (bipolar junction transistor) is disclosed. Conventional front end processes are used to form an N+ layer on a substrate. An N-type collector region is then formed followed by formation of isolation regions on the substrate surface. A deep collection connector region is formed by ion implantation into the N-well. Next, a P base region is formed by ion implantation. An undoped polysilicon (polycide) layer is then deposited on the surface of the substrate. Thereafter, a dielectric layer, which preferably cannot be oxidized, is deposited on top of the undoped polysilicon (polycide) layer. The dielectric layer is then patterned to form a dielectric emitter. Nitride spacers are then formed on the sidewalls of the dielectric emitter. The polysilicon (polycide) layer is then heavily doped with P-type impurities except in the area of the dielectric emitter and nitride spacers.

Abstract: The present invention provides a method to achieve shallow trench isolation (STI) on the quarter-micron scale. A thin oxide layer, a thick nitride layer, a thick oxide layer and a thin nitride layer are formed sequentially on a silicon substrate. A photo-resist (PR) layer is then applied as a mask for the isolation regions. The top nitride layer, the top oxide layer and the bottom nitride layer are then etched away from the areas not covered by the PR layer. The PR layer is then removed. An isotropic oxide etch is then applied to create a recess along the bottom oxide layer. A thin oxide layer is then grown on the exposed silicon surface. A thin nitride layer is then deposited to fill the recess in the bottom oxide layer. An anisotropic nitride etch is applied to form a nitride spacer along the isolation edge. A thick oxide layer is then grown and removed. This step is repeated as necessary to obtain the desired trench slope.

Abstract: A self aligned lateral BJT is disclosed which has a lightly doped first region of a first conductivity type, e.g., P-type. A heavily doped poly region, of a second conductivity type, e.g., N-type, is provided on a portion of a surface of the first region. A heavily doped second region of the second conductivity type, is disposed in the first region below the poly region. An oxide region is provided on a portion of the first region surface adjacent to the poly region. A third region of the first conductivity type is disposed in the first region adjacent to the second region and below the oxide region. A heavily doped fourth region of the second conductivity type is disposed in the first region adjacent to the third region. The fabrication of the lateral BJT includes the step of forming a poly region on a portion of the first region. Then, the second region is formed by diffusing an impurity from the poly region into the first region. The third region is then formed adjacent to the second region.

Abstract: A method for making a variable length LDD spacer structure is disclosed. A first insulation layer (i.e., gate oxide) is formed on a semiconductor device having a P-well and an N-well provided in a substrate. A first and a second polysilicon gate are formed on the P-well and the N-well respectively wherein the first insulation layer is interposed between the wells and the gates. A second insulation layer is formed over the first and second gates. N-type impurity ions are selectively implanted to form lightly doped N-type diffusion regions in the P-well. Similarly, P-type impurity ions are selectively implanted to form lightly doped P-type diffusion regions in the N-well. A polysilicon spacer is formed on both side walls of each of the gates. Each spacer covers a portion of the lightly doped N-type and P-type diffusion regions. N-type impurity ions are selectively implanted in a portion of the lightly doped N-type diffusion regions not covered by the spacers.

Abstract: An ESD protection device is disclosed having a first region of a first conductivity type. A second region, which is heavily doped, of a second conductivity type is disposed in the first region. The second region extends from the surface of the first region a first depth. A third region, which is heavily doped, of the second conductivity type, is also disposed in the first region such that the third region is separated from the second region by a portion of the surface of the first region. The third region extends from the surface of the first region a second depth less than the first depth of the second region. An insulating region is grown on a portion of the surface of the first region between the second and third regions. Furthermore, a resistive conducting region is disposed on the second region and the insulating region. A portion of the resistive conducting region extends beyond the second region for receiving an input signal.

Abstract: An ESD protection device is disclosed having a first region of a first conductivity type. A second region, which is heavily doped, of a second conductivity type is disposed in the first region. The second region extends from the surface of the first region a first depth. A third region, which is heavily doped, of the second conductivity type, is also disposed in the first region such that the third region is separated from the second region by a portion of the surface of the first region. The third region extends from the surface of the first region a second depth less than the first depth of the second region. An insulating region is grown on a portion of the surface of the first region between the second and third regions. Furthermore, a resistive conducting region is disposed on the second region and the insulating region. A portion of the resistive conducting region extends beyond the second region for receiving an input signal.