Abstract: A method of transitioning a port in a communication system from an active state to a standby state includes the steps of transmitting a signal to transition the port to the standby state, and, upon transmission of the signal to transition the port to the standby state, transitioning the port from the active state into the standby state without entering a suspended state. The port may be a physical layer interface port and the communication system may be an IEEE 1394-compliant communication system.

Abstract: A flash memory device, includes a case (1) having a chamber and an opening (1120) at one end thereof. A memory module (2) is received in the chamber and has a plug (22) formed at one end thereof. A pole (3) has a first portion (30) received in the chamber to drive the plug of the memory module moving in or out of the opening, and a second portion (31) opposite to the first portion. A revolver mechanism (5) has a main body (51) which is rotatable, and a spindle (52) assembled to the main body and rotatablely coupled to the second portion to drive the pole moving along a linear direction.

Abstract: A device (100) for enclosing a flash memory module includes a first shell (1) having a groove (13), and an outer wall (14) covering the groove and having an reduced opening (142) communicating with the groove. An attachment mechanism (4) coupled to the first shell comprises a retaining member (42) having a base portion (421) retained in the groove and an engaging portion (422) extending from the base portion and through the opening outwardly, and a ring (41) coupled to the engaging portion of the retaining member. The base portion is abutted against by the outer wall.

Abstract: A flash memory device (8) includes a memory module (2), a screw (3), a gear (4) and a case (1). The memory module (2) has a plug (22) formed at one end thereof. The screw (3) has a first end (30) and a second end (31) opposite to the first end (30). The first end (30) is mounted on the memory module (2). The gear (4) is positioned on the screw (3) and is rotatable relative to the screw (3). The case (1) includes a receiving cavity for receiving the memory module (2), and a first inner case (10) with a first rack (1002) engaging with one side of the gear (4). The first rack (1002) extends along a length direction of the case (1). The memory module (2) has a second rack (2011) engaging with another side of the gear (4). The second rack (2011) extends along the length direction too. The screw (3) is located between the first rack (1002) and the second rack (2011).

Abstract: A flash memory device includes a main body, a cover and an elastic member connecting the main body and the cover. The main body includes a hinge protrusion formed thereon. The cover includes a tail and a pair of parallel plates facing each other and spaced by an interval corresponding to a thickness of the main body. At least one plate defines an opening for receiving the hinge protrusion so that the cover is rotatable with respect to the main body. The elastic member is fastened to the cover to abut against the protrusion, or fastened to the main body to abut against the cover, when the cover is rotatable relative to the main body.

Abstract: A flash memory device includes a bottom shell, a PCB mounted on the bottom shell, a connector interface electrically connecting the PCB, a movable cover covering the PCB and a light-guiding member set on the cover. The PCB includes a LED light. The light-guiding member absorbs the light of the LED light in order to averagely illuminate an area of the cover to be illuminated.

Abstract: A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.

Abstract: A method and apparatus for detecting the C-bit parity application of DS3 makes use of the relative state of the CP-bits and the P-bits in one or more M-frames alone or in combination with the state of the AIC signal. In one implementation, the invention is a detector circuit that is adapted to receive a CP-bit and a P-bit from each of a group of one or more M-frames of a DS3 service. For each M-frame in the group, the detector circuit performs a logical XOR between the CP-bit and the P-bit for that M-frame. The detector circuit further performs a logical OR between the XOR results from each M-frame in the group and outputs a C-bit parity format detect signal if the result is zero.

Abstract: A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.

Abstract: A method of transitioning a port in a communication system from an active state to a standby state includes the steps of transmitting a signal to transition the port to the standby state, and, upon transmission of the signal to transition the port to the standby state, transitioning the port from the active state into the standby state without entering a suspended state. The port may be a physical layer interface port and the communication system may be an IEEE 1394-compliant communication system.

Abstract: A flash memory device includes a main body, a cover and an elastic member connecting the main body and the cover. The main body includes a hinge protrusion formed thereon. The cover includes a tail and a pair of parallel plates facing each other and spaced by an interval corresponding to a thickness of the main body. At least one plate defines an opening for receiving the hinge protrusion so that the cover is rotatable with respect to the main body. The elastic member is fastened to the cover to abut against the protrusion, or fastened to the main body to abut against the cover, when the cover is rotatable relative to the main body.

Abstract: A read activity detector circuit for use in a random access memory array includes a plurality of synchronizer circuits operative to receive a plurality of respective reference clock signals having a frequency that is substantially the same as a core reference clock and having different phases relative to one another. Each of the synchronizer circuits, in response to a first control signal presented thereto, generates an output signal having a rising edge or a falling edge which is substantially aligned to a rising edge or a falling edge of the reference clock signal corresponding thereto. The activity detector circuit further includes a controller operative to receive the respective output signals from the plurality of synchronizer circuits and to generate an output signal as a function thereof which is indicative of data to be read from the random access memory array.

Abstract: The present invention provides a thermosensitive and biodegradable microgel and a method of synthesizing such microgels. The thermosensitive and biodegradable microgel is synthesized from a macromer comprising a thermosensitive block polymer co-polymerized with a biodegradable moiety encapped with a cross-linkable or polymerizable moiety at either end. The microgels of the present invention are synthesized by inverse suspension polymerization of the macromers. The microgels are biodegradable into components that are non-toxic and easily removed from the body. The microgel of the present invention is temperature sensitive and is “intelligent” as well as biodegradable. The microgels are preferably used for the controlled release of a drug or in tissue engineering. Most preferably, the microgels are suitable for the control release of biologically active substances such as proteins.

Abstract: The present invention provides a thermosensitive and biodegradable microgel and a method of synthesizing such microgels. The thermosensitive and biodegradable microgel is synthesized from a macromer comprising a thermosensitive block polymer co-polymerized with a biodegradable moiety encapped with a cross-linkable or polymerizable moiety at either end. The microgels of the present invention are synthesized by inverse suspension polymerization of the macromers. The microgels are biodegradable into components that are non-toxic and easily removed from the body. The microgel of the present invention is temperature sensitive and is “intelligent” as well as biodegradable. The microgels are preferably used for the controlled release of a drug or in tissue engineering. Most preferably, the microgels are suitable for the control release of biologically active substances such as proteins.

Abstract: A read activity detector circuit for use in a random access memory array includes a plurality of synchronizer circuits operative to receive a plurality of respective reference clock signals having a frequency that is substantially the same as a core reference clock and having different phases relative to one another. Each of the synchronizer circuits, in response to a first control signal presented thereto, generates an output signal having a rising edge or a falling edge which is substantially aligned to a rising edge or a falling edge of the reference clock signal corresponding thereto. The activity detector circuit further includes a controller operative to receive the respective output signals from the plurality of synchronizer circuits and to generate an output signal as a function thereof which is indicative of data to be read from the random access memory array.

Abstract: A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.

Abstract: A method for seasoning a chamber and depositing a low dielectric constant layer on a substrate in the chamber is provided. In one aspect, the method includes seasoning the chamber with a first mixture comprising one or more organosilicon compounds and one or more oxidizing gases and depositing a low dielectric constant layer on a substrate in the chamber from a second mixture comprising one or more organosilicon compounds and one or more oxidizing gases, wherein a ratio of the total flow rate of the organosilicon compounds to the total flow rate of the oxidizing gases in the first mixture is lower than the total flow rate of the organosilicon compounds to the total flow rate of the oxidizing gases in the second mixture.

Abstract: A cryogenic current limiting fuse is disclosed together with a method of manufacturing a cryogenic current limiting fuse, the cryogenic current limiting fuse comprising a first cryogenic composite and a second cryogenic composite wherein at least one of the first and the second cryogenic composites has a non-linear and increasing resistivity with respect to at least one of temperature and current.

Abstract: According to one embodiment of the invention, a method of modifying a mechanical, physical and/or electrical property of a dielectric layer comprises exposing the dielectric layer to a first dose of electron beam radiation at a first energy level; and thereafter, exposing the dielectric layer to a second dose of electron beam radiation at a second energy level that is different from the first energy level.

Abstract: A method and apparatus for detecting the C-bit parity application of DS3 makes use of the relative state of the CP-bits and the P-bits in one or more M-frames alone or in combination with the state of the AIC signal. In one implementation, the invention is a detector circuit that is adapted to receive a CP-bit and a P-bit from each of a group of one or more M-frames of a DS3 service. For each M-frame in the group, the detector circuit performs a logical XOR between the CP-bit and the P-bit for that M-frame. The detector circuit further performs a logical OR between the XOR results from each M-frame in the group and outputs a C-bit parity format detect signal if the result is zero.