Patents by Inventor Wen Zhu

Wen Zhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060018346
    Abstract: A method and apparatus for detecting the C-bit parity application of DS3 makes use of the relative state of the CP-bits and the P-bits in one or more M-frames alone or in combination with the state of the AIC signal. In one implementation, the invention is a detector circuit that is adapted to receive a CP-bit and a P-bit from each of a group of one or more M-frames of a DS3 service. For each M-frame in the group, the detector circuit performs a logical XOR between the CP-bit and the P-bit for that M-frame. The detector circuit further performs a logical OR between the XOR results from each M-frame in the group and outputs a C-bit parity format detect signal if the result is zero.
    Type: Application
    Filed: July 21, 2004
    Publication date: January 26, 2006
    Inventor: Wen Zhu
  • Publication number: 20050227499
    Abstract: A method for seasoning a chamber and depositing a low dielectric constant layer on a substrate in the chamber is provided. In one aspect, the method includes seasoning the chamber with a first mixture comprising one or more organosilicon compounds and one or more oxidizing gases and depositing a low dielectric constant layer on a substrate in the chamber from a second mixture comprising one or more organosilicon compounds and one or more oxidizing gases, wherein a ratio of the total flow rate of the organosilicon compounds to the total flow rate of the oxidizing gases in the first mixture is lower than the total flow rate of the organosilicon compounds to the total flow rate of the oxidizing gases in the second mixture.
    Type: Application
    Filed: April 2, 2004
    Publication date: October 13, 2005
    Inventors: Sohyun Park, Wen Zhu, Tzu-Fang Huang, Li-Qun Xia, Hichem M'Saad
  • Publication number: 20050146817
    Abstract: A cryogenic current limiting fuse is disclosed together with a method of manufacturing a cryogenic current limiting fuse, the cryogenic current limiting fuse comprising a first cryogenic composite and a second cryogenic composite wherein at least one of the first and the second cryogenic composites has a non-linear and increasing resistivity with respect to at least one of temperature and current.
    Type: Application
    Filed: December 31, 2003
    Publication date: July 7, 2005
    Inventors: Julian Cave, Andre Hamel, Vijay Sood, Dan Watson, Wen Zhu
  • Publication number: 20040156906
    Abstract: The present invention provides a thermosensitive and biodegradable microgel and a method of synthesizing such microgels. The thermosensitive and biodegradable microgel is synthesized from a macromer comprising a thermosensitive block polymer co-polymerized with a biodegradable moiety encapped with a cross-linkable or polymerizable moiety at either end. The microgels of the present invention are synthesized by inverse suspension polymerization of the macromers. The microgels are biodegradable into components that are non-toxic and easily removed from the body. The microgel of the present invention is temperature sensitive and is “intelligent” as well as biodegradable. The microgels are preferably used for the controlled release of a drug or in tissue engineering. Most preferably, the microgels are suitable for the control release of biologically active substances such as proteins.
    Type: Application
    Filed: January 20, 2004
    Publication date: August 12, 2004
    Inventors: Jiandong Ding, Wen Zhu, Biaobing Wang, Ying Zhang
  • Publication number: 20040157453
    Abstract: A method of fabricating an interconnect structure comprising etching a via into an upper low K dielectric layer and into a hardened portion of a lower low K dielectric layer. The via is defined by a pattern formed in a photoresist layer. The photoresist layer is then stripped, and a trench that circumscribes the via as defined by a hard mask is etched into the upper low K dielectric layer and, simultaneously, the via that was etched into the hardened portion of the lower low K dielectric layer is further etched into the lower low K dielectric layer. The result is a low K dielectric dual damascene structure.
    Type: Application
    Filed: December 22, 2003
    Publication date: August 12, 2004
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Gerardo A. Delgadino, Yan Ye, Neungho Shin, Yunsang Kim, Li-Qun Xia, Tzu-Fang Huang, Lihua Li Huang, Joey Chiu, Xiaoye Zhao, Fang Tian, Wen Zhu, Ellie Yieh