Abstract: The present disclosure relates to an electronic apparatus, a wireless communication method and a computer-readable medium. The electronic apparatus for wireless communication according to one embodiment comprises a processing circuit. The processing circuit is configured to perform control to send or receive configuration information. The configuration information is related to configuration of a reference signal used in a discovery process of an integrated access backhaul (IAB) link node.

Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate, at least one group of contact pads, a plurality of first light-emitting elements, a plurality of first pixel driving circuits, a plurality of connecting traces, a plurality of data lines and a plurality of leads. The display area includes a first display area and a second display area; the first light-emitting elements are located in the first display area; the first pixel driving circuits are located in the second display area; the leads are located in the first display area and the peripheral area, and connect the data lines and the at least one group of contact pads; orthographic projections of the first light-emitting elements on a substrate surface of the base substrate are at least partly overlapped with orthographic projections of the leads on the substrate surface of the base substrate.

Abstract: The present disclosure relates to an electronic apparatus, a wireless communication method and a computer-readable medium. According to one embodiment, an electronic apparatus for wireless communication comprises: a processing circuit configured to: determine whether a first user equipment satisfies a condition for performing direct link communication with a second user equipment by using an unlicensed frequency band resource; and if the condition is satisfied, control the first user equipment to perform direct link communication with the second user equipment by using the unlicensed frequency band resource.

Abstract: A control circuit for an isolated power converter includes a first sensing circuit that senses a secondary side output voltage and produces a pulse wave modulation (PWM) signal having a duty cycle that is proportional to a value of the secondary side output voltage. The PWM is transferred across the converter isolation barrier to the primary side, and a primary side circuit receives the PWM signal and outputs a control signal. A controller determines the value of the secondary side output voltage from the control signal and uses the value to control primary side power switching devices of the isolated power converter to regulate the secondary side output voltage at a selected value.

Abstract: Disclosed in the present disclosure is a double-deck multi-span bridge construction method. According to the double-deck bridge construction method of the present disclosure, construction is carried out by using a method of disassembling a support jig frame in a graded and span-separated mode, an upper chord jig frame and a lower chord jig frame can be used in a recycle manner, and construction costs are reduced. In addition, a construction period of building the support jig frame is shortened, and other construction operations can be synchronously carried out on a span in which the jig frame is disassembled, for example, fire retardant coating construction can be carried out on a mounted bridge deck after the jig frame is disassembled, and the construction period of a double-deck multi-span bridge is effectively shortened.

Abstract: A display substrate, includes: a display region. The display region includes a plurality of sub-pixels disposed on a substrate, a plurality of first signal lines extending in a first direction, and a plurality of data lines extending in a second direction. At least one sub-pixel includes a driving circuit, and the driving circuit includes a plurality of transistors and at least one storage capacitor. The transistor at least includes a first conductive layer and a second conductive layer. The plurality of first signal lines is located in a third conductive layer. The third conductive layer is located on a side of a control electrode of a transistor of the driving circuit away from the substrate.

Abstract: A display substrate and a display device. The display substrate includes a base substrate and a plurality of sub-pixels on the base substrate, each sub-pixel includes a pixel circuit, and the pixel circuit includes a drive sub-circuit and a first reset sub-pixel. The first reset sub-pixel is configured to apply a first reset voltage to a control terminal of the drive sub-circuit in response to a first reset control voltage; the display substrate further comprises a first reset signal line electrically connected with the first terminal of the first reset sub-circuit to provide the first reset voltage, and the first reset signal line is in a semiconductor layer and comprises a doped semiconductor material.

Abstract: A display substrate and a drive method thereof and a display device. The display substrate includes a base substrate and a plurality of sub-pixels on the base substrate, each sub-pixel includes a pixel circuit, and the pixel circuit includes a first reset sub-pixel. The first reset sub-pixel is configured to apply a first reset voltage to a light-emitting element in response to a first reset control voltage to reversely bias the light-emitting element.

Abstract: A display substrate, a preparation method thereof, and a display device are provided. The display substrate includes: a substrate, and a drive structure layer and a light-emitting structure layer that are sequentially stacked on the substrate and located in a display region. The display substrate further includes: M rows of scanning signal lines and M rows of light-emitting signal lines. The light-emitting structure layer includes: M rows and N columns of light-emitting structures. The drive structure layer includes: a pixel circuit array and a drive circuit array that extend in a column direction. The pixel circuit array and the drive circuit array are sequentially arranged in a row direction. The pixel circuit array includes: M rows and N columns of pixel circuits, and the pixel circuits are in one-to-one correspondence with the light-emitting structures and electrically connected to corresponding light-emitting structures.

Abstract: The embodiments of the present disclosure provide an array substrate and a related display panel and a related display device. An array substrate includes a plurality of pairs of scan signal lines. A first scan signal line of the m-th pair of scan signal lines is configured to provide a first scan signal to a sub-pixel in a (2n?1)-th column from sub-pixels in the m-th. And a plurality of pairs of driving reset control signal lines. A second driving reset control signal line of the m-th pair of driving reset control signal lines is configured to provide a second driving reset control signal to the sub-pixel in the 2n-th column from the sub-pixels in the m-th row. The m and n are integers greater than or equal to 1. In the embodiments of the present disclosure, the first scan signal line of the m-th pair of scan signal lines and the second driving reset control signal line of the m-th pair of driving reset control signal lines are the same signal line.

Abstract: A display substrate and a display device are provided. The display substrate includes: a plurality of sub-pixels; a first electrode layer including a plurality of anode structures; and a pixel definition layer located on a side of the first electrode layer away from the base substrate and including a plurality of openings. For at least some sub-pixels, an orthographic projection of the opening of each sub-pixel falls into that of the anode structure of the sub-pixel on the base substrate, a figure of the orthographic projection of the opening of each sub-pixel has a different shape from a figure of the orthographic projection of the anode structure of the sub-pixel on the base substrate. The figure of the orthographic projection of the anode structure of each sub-pixel has more symmetry axis than the figure of the orthographic projection of the opening of the sub-pixel on the base substrate.

Abstract: A display substrate, including: a display region and a peripheral region located on the periphery of the display region. A scan driver circuit is disposed in the peripheral region. A plurality of sub-pixels, and a plurality of first signal lines that are connected to the scan driver circuit and extend in a first direction, are disposed in the display region. The display region includes: a substrate, and a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer that are sequentially disposed on the substrate. The third conductive layer comprises: a plurality of first signal lines, and first electrodes and second electrodes of a plurality of transistors. An insulating layer between the third conductive layer and the first conductive layer is provided with first via holes.

Abstract: A pixel structure, a driving method thereof and a display device are disclosed. The pixel structure includes: a pixel circuit and a plurality of light emitting devices; the pixel circuit has a plurality of display periods, each display period includes: a first reset stage, a data write stage, a second reset stage and a light emitting stage, the driving method includes: in the second reset stage, providing a valid level signal to at least one second reset line to cause the corresponding second reset sub-circuit to write a voltage on the initialization signal line into a first electrode of the light emitting device; in the light emitting stage, providing a valid level signal to a first light emitting control line and providing a valid level signal to at least one second light emitting control line.

Abstract: A display substrate, a preparation method thereof, and a display device are provided. The display substrate includes: a substrate, and a drive structure layer and a light-emitting structure layer that are sequentially stacked on the substrate and located in a display region. The display substrate further includes: M rows of scanning signal lines and M rows of light-emitting signal lines. The light-emitting structure layer includes: M rows and N columns of light-emitting structures. The drive structure layer includes: a pixel circuit array and a drive circuit array that extend in a column direction. The pixel circuit array and the drive circuit array are sequentially arranged in a row direction. The pixel circuit array includes: M rows and N columns of pixel circuits, and the pixel circuits are in one-to-one correspondence with the light-emitting structures and electrically connected to corresponding light-emitting structures.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a substrate, a plurality of initialization signal lines, in the display area of the substrate, the plurality of initialization signal lines extend in a first direction; an interlayer insulating layer, on a side of the plurality of initialization signal lines facing away from the substrate; and a plurality of auxiliary signal lines, on a side of the interlayer insulating layer facing away from the substrate and in the display area, the plurality of auxiliary signal lines extend in a second direction, and the first direction is different from the second direction; the plurality of auxiliary signal lines and the plurality of initialization signal lines are electrically connected to each other through first vias, the first vias run through the interlayer insulating layer.

Abstract: A display substrate and a drive method thereof and a display device. The display substrate includes a base substrate and a plurality of sub-pixels on the base substrate, each sub-pixel includes a pixel circuit, and the pixel circuit includes a first reset sub-pixel. The first reset sub-pixel is configured to apply a first reset voltage to a light-emitting element in response to a first reset control voltage to reversely bias the light-emitting element.

Abstract: The present disclosure relates to an array substrate and a display panel and a display device thereof. The array substrate comprises: a substrate; a pixel array disposed on the substrate, comprising a plurality of sub-pixels arranged in a plurality of rows and a plurality of columns; a plurality of pairs of scan signal lines, extending in a row direction and being spaced apart from each other in a column direction; and a reset voltage source signal line and a data signal line, extending in the column direction.

Abstract: A flexible display panel and a preparation method therefor, a display apparatus, and a tiled display apparatus. The flexible display panel is provided with a display area and a peripheral area located on the periphery of the display area, the peripheral area comprising at least one bent area and a folded area located on a side of each bent area away from the display area. The flexible display panel comprises: a flexible substrate and a frame circuit that is disposed on the flexible substrate and is located in the peripheral area, at least a portion of the frame circuit being located in the folded area. The portion of the flexible display panel that is located in the folded area is configured to, by means of the portion located in the bent area, be folded in the direction away from the display side of the flexible display panel.

Abstract: A display substrate, including: a display region and a peripheral region located on the periphery of the display region. A scan driver circuit is disposed in the peripheral region. A plurality of sub-pixels, and a plurality of first signal lines that are connected to the scan driver circuit and extend in a first direction, are disposed in the display region. The display region includes: a substrate, and a semiconductor layer, a first conductive layer, a second conductive layer and a third conductive layer that are sequentially disposed on the substrate. The third conductive layer comprises: a plurality of first signal lines, and first electrodes and second electrodes of a plurality of transistors. An insulating layer between the third conductive layer and the first conductive layer is provided with first via holes.