Abstract: An internal rotor type nail drive device of electric nail gun, comprising a nailing rod and an internal rotor type rotary actuator that can output a specific rotation angle and can drive the nailing rod to move downward for nailing. Specifically, the rotary actuator comprises a stator and a rotor arranged inside the stator, even groups of electromagnetic mutual action components are configured in pairs between the stator and the rotor, to generate a tangential force to drive the rotor to rotate for a specific rotation angle, and to drive the nailing rod to move for a nailing stroke. The nailing stroke can be determined by a specific rotation angle. Thus, through the above configuration of the rotary actuator, the structure of the electric nail gun can be simplified, and the kinetic energy for nailing can be increased.

Abstract: A heat dissipation system of an electronic device including a body, a plurality of heat sources disposed in the body, and at least one centrifugal heat dissipation fan disposed in the body is provided. The centrifugal heat dissipation fan includes a housing and an impeller disposed in the housing on an axis. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions, and the plurality of outlets respectively correspond to the plurality of heat sources.

Abstract: A centrifugal heat dissipation fan of a portable electronic device. The centrifugal heat dissipation fan includes a hub, multiple metal blades, and at least one ring. The metal blades are disposed surrounding the hub. The metal blades include multiple radial dimensions, and the structure of the metal blade with a shorter radial dimension is a part of the structure of the metal blade with a longer radial dimension. The metal blades having different radial dimensions form at least two ring areas, and the distribution numbers of the metal blades in the at least two ring areas are different from each other. The ring surrounds the hub and connects the metal blades.

Abstract: A centrifugal heat dissipation fan including a housing and an impeller is provided. The housing has at least one inlet disposed along an axis and at least one first outlet and a second outlet located in different radial directions, wherein the first outlet and the second outlet are opposite to and separated from each other. The impeller is disposed in the housing along the axis. A heat dissipation system of an electronic device is also provided.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first transistor, a first resistive random access memory (RRAM) resistor, and a second RRAM resistor. The first resistor includes a first resistive material layer, a first electrode shared by the second resistor, and a second electrode. The second resistor includes the first electrode, a second resistive material layer, and a third electrode. The first electrode is electrically coupled to the first transistor.

Abstract: A centrifugal heat dissipation fan including a housing and an impeller disposed in the housing on an axis is provided. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions. A heat dissipation system of an electronic device is also provided.

Abstract: The present disclosure provides a thin film including a first thermoplastic polyolefin (TPO) elastomer which is anhydride-grafted. The present disclosure further provides a method for manufacturing the thin film, a laminated material and a method for adhesion.

Abstract: A method to control a memory cell in a memory device, where the memory cell includes a switch, a memory element, and a negative resistance device coupled in series, the method includes: determine whether the memory cell is in a read operation or not; during the read operation in the memory cell, apply a read voltage greater than a predetermined threshold voltage of the negative resistance device for making the negative resistance device entering into a negative resistance state. A memory device that includes a memory cell array is also provided.

Abstract: A method to control a memory cell in a memory device, where the memory cell includes a switch, a memory element, and a negative resistance device coupled in series, the method includes: determine whether the memory cell is in a read operation or not; during the read operation in the memory cell, apply a read voltage greater than a predetermined threshold voltage of the negative resistance device for making the negative resistance device entering into a negative resistance state. A memory device that includes a memory cell array is also provided.

Abstract: A semiconductor substrate is provided. The semiconductor substrate has thereon a first dielectric layer, at least one conductive pattern disposed in the first dielectric layer, and a second dielectric layer covering the first dielectric layer and the at least one conductive pattern. A via opening is formed in the second dielectric layer. The via opening exposes a portion of the at least one conductive pattern. A polish stop layer is conformally deposited on the second dielectric layer and within the via opening. A barrier layer is conformally deposited on the polish stop layer. A tungsten layer is conformally deposited on the barrier layer. The tungsten layer and the barrier layer are polished until the polish stop layer on the second dielectric layer is exposed, thereby forming a via plug in the via opening. A bottom electrode layer is conformally deposited on the second dielectric layer and the via plug.

Abstract: A semiconductor substrate is provided. The semiconductor substrate has thereon a first dielectric layer, at least one conductive pattern disposed in the first dielectric layer, and a second dielectric layer covering the first dielectric layer and the at least one conductive pattern. A via opening is formed in the second dielectric layer. The via opening exposes a portion of the at least one conductive pattern. A polish stop layer is conformally deposited on the second dielectric layer and within the via opening. A barrier layer is conformally deposited on the polish stop layer. A tungsten layer is conformally deposited on the barrier layer. The tungsten layer and the barrier layer are polished until the polish stop layer on the second dielectric layer is exposed, thereby forming a via plug in the via opening. A bottom electrode layer is conformally deposited on the second dielectric layer and the via plug.

Abstract: A magnetoresistive random access memory (MRAM) includes a plurality of input/output units. Each input/output units can read and write memory cells simultaneously. So a read/write column to column delay time (tCCD) of the MRAM is equal to or shorter than a read/write column to column delay time of a dynamic random access memory (DRAM). Consequently, a data-rate of the MRAM is equal to or shorter than a data-rate of the DRAM.

Abstract: A magnetoresistive random access memory (MRAM) includes a plurality of input/output units. Each input/output units can read and write memory cells simultaneously. So a read/write column to column delay time (tCCD) of the MRAM is equal to or shorter than a read/write column to column delay time of a dynamic random access memory (DRAM). Consequently, a data-rate of the MRAM is equal to or shorter than a data-rate of the DRAM.

Abstract: A method of forming a gate includes the following steps. A gate structure is formed on a substrate. An etch stop layer is formed on the gate structure and the substrate. A dielectric layer is formed to cover the etch stop layer. The dielectric layer is planarized to form a planarized top surface of the dielectric layer and expose a portion of the etch stop layer on the gate structure. An oxygen containing treatment is performed to form an oxygen containing layer on the exposed etch stop layer. A deposition process is performed to form an oxide layer covering the planarized top surface of the dielectric layer and the oxygen containing layer.

Abstract: A method to control a memory cell in a memory device, where the memory cell includes a switch, a memory element, and a negative resistance device coupled in series, the method includes: determine whether the memory cell is in a read operation or not; during the read operation in the memory cell, apply a read voltage greater than a predetermined threshold voltage of the negative resistance device for making the negative resistance device entering into a negative resistance state. A memory device that includes a memory cell array is also provided.

Abstract: A method to control a memory cell in a memory device, where the memory cell includes a switch, a memory element and a negative resistance device coupled in series, the method includes: determine whether the memory cell is in a read operation or not; during the read operation in the memory cell, apply a read voltage greater than a predetermined threshold voltage of the negative resistance device for making the negative resistance device entering into a negative resistance state. A memory device that includes a memory cell array is also provided.

Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.

Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.

Abstract: A method to control a memory cell in a memory device, where the memory cell includes a switch, a memory element and a negative resistance device coupled in series, the method includes: determine whether the memory cell is in a read operation or not; during the read operation in the memory cell, apply a read voltage greater than a predetermined threshold voltage of the negative resistance device for making the negative resistance device entering into a negative resistance state. A memory device that includes a memory cell array is also provided.

Abstract: A hydrogen sensing device includes a multi-layered structure member. The multi-layered structure member includes a stack of alternatingly disposed magnetic layers and non-ferromagnetic layers. One of the magnetic layers is a topmost layer of the multi-layered structure member. The topmost layer includes a palladium-based material to detect hydrogen.