Patents by Inventor Wendy Belluomini
Wendy Belluomini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090083504Abstract: A data storage method comprises storing first data in at least a first data chunk, wherein the first data chunk is a logical representation of one or more sectors on at least a first disk drive in a storage system; storing first metadata, associated with the first data, in at least a first appendix, wherein the first appendix is a logical representation of a sector region on at least the first disk drive in the storage system, and wherein the first metadata comprises first atomicity metadata (AMD) and first validity metadata (VMD) associated with the first data; and storing a copy of the first VMD for the first data in at least one low latency non-volatile storage (LLNVS) device.Type: ApplicationFiled: September 24, 2007Publication date: March 26, 2009Inventors: Wendy Belluomini, John Edward Bish, Kenneth Day, III, James Hafner, Bret S. Weber
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Publication number: 20080282105Abstract: Data validation systems and methods are provided. Data is recorded in N data chunks on one or more storage mediums. A first validation chunk independently associated with said N data chunks comprises first validation information for verifying accuracy of data recorded in said N data chunks. The first validation chunk is associated with a first validation appendix comprising second validation information, wherein the first validation appendix is stored on a first storage medium independent of said one or more storage mediums.Type: ApplicationFiled: May 10, 2007Publication date: November 13, 2008Inventors: Veera W. Deenadhayalan, James L. Hafner, James C. Wyllie, Wendy A. Belluomini
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Publication number: 20080010333Abstract: A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit.Type: ApplicationFiled: July 11, 2007Publication date: January 10, 2008Inventors: Wendy Belluomini, Hung Ngo, Jun Sawada
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Publication number: 20070244954Abstract: A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit.Type: ApplicationFiled: February 1, 2007Publication date: October 18, 2007Inventors: Wendy Belluomini, Hung Ngo, Jun Sawada
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Patent number: 7284029Abstract: A 4-to-2 carry save adder using limited switching dynamic logic (LSDL) to reduce power consumption while reducing the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a first LSDL circuit configured to output a sum bit. The carry save adder may further include a second LSDL circuit configured to output a carry bit. Both the first and second LSDL circuits use a carry generated in the current stage that was previously generated in the previous stage (next lower order bit position). Since the carry is generated in the current stage and not in the previous stage, the delay in outputting the sum and carry bits is reduced and hence the performance of carry save adders is improved. Further, since LSDL circuits were used in the carry save adder, power consumption was reduced while using a small amount of area.Type: GrantFiled: November 6, 2003Date of Patent: October 16, 2007Assignee: International Business Machines CorporationInventors: Wendy A. Belluomini, Ramyanshu Datta, Chandler T. McDowell, Robert K. Montoye, Hung C. Ngo
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Patent number: 7216141Abstract: A 4-to-2 carry save adder with a reduction in the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a lower order full order coupled to a higher order full adder. The carry save adder may further include a logic unit coupled to the higher order full adder where the logic unit is configured to generate a carry bit to be inputted to the higher order full adder that normally would be generated from the carry save adder located in the previous stage. By generating this carry bit (carry-in bit) in the current stage and not in the previous stage, the delay of the carry-in bit inputted to the higher order full adder is reduced thereby reducing the delay of outputting the sum and carry bits by the higher order full adder.Type: GrantFiled: November 6, 2003Date of Patent: May 8, 2007Assignee: International Business Machines CorporaitonInventors: Wendy A. Belluomini, Ramyanshu Datta, Jente Benedict Kuang, Chandler T. McDowell, Robert K. Montoye, Hung C. Ngo
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Publication number: 20060290385Abstract: A dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock controlled provides increased noise immunity in dynamic digital circuits. By clocking the pre-charge element with a signal having a reduced swing in the voltage direction that turns off the pre-charge element, the pre-charge element provides a small current that prevents the dynamic summing node of a gate from erroneously evaluating due to noise, and eliminates the need for a keeper device. Providing the reduced-swing asymmetric clock as a separate signal prevents performance degradation in the rest of the circuit. Specifically, the foot devices in the dynamic portion of the circuit are controlled with the full swing clock so that evaluation is not compromised by noise or slowed. Foot and pull-up devices in any static portion of the circuit are also controlled with the full-swing clock so that switching speed and leakage immunity are not affected.Type: ApplicationFiled: June 28, 2005Publication date: December 28, 2006Inventors: Wendy Belluomini, Robert Montoye, Aniket Saha
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Publication number: 20060290382Abstract: A method and apparatus for power consumption reduction in a limited-switch dynamic logic (LSDL) circuit provides reduced power consumption by reducing clock power dissipation. By clocking LSDL gates with a clock signal having a reduced voltage swing in the evaluation phase, the LSDL gates are permitted to operate, while reducing the clock power consumption dramatically. Since clock power consumption dominates in LSDL circuits, the reduction in clock power dissipation results in a significant reduction in overall circuit power consumption. The reduced swing clock is produced at a plurality of local clock buffers by supplying the local clock buffers with an extra power supply rail that is switched onto the clock distribution lines by the local clock buffers in response to the full-swing evaluate phase clock received from the global clock distribution network by the local clock buffers.Type: ApplicationFiled: June 28, 2005Publication date: December 28, 2006Inventors: Wendy Belluomini, Aniket Saha
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Publication number: 20050195042Abstract: A method and ring oscillator circuit for measuring circuit delays over a wide operating range permits improved analysis of dynamic circuits. A pulse generator circuit provides a pulse to an input of a dynamic circuit under test, which may be a pre-charge or evaluation pulse that is triggered by a transition of an output of the dynamic circuit that occurs during the state opposite that of the state commanded by the pulse. The action of the circuit provides for measuring any amount of delay to the next transition in the opposite state irrespective of the pulse width. By providing a wide-range of operation, characteristics such as leakage, charge sharing, data dependent node capacitance, previous value dependence as well as other dynamic circuit behaviors may be determined. The ring oscillator circuit includes an enable start circuit that causes a first pulse to be generated by the one-shot when the ring oscillator circuit is enabled.Type: ApplicationFiled: March 4, 2004Publication date: September 8, 2005Applicant: International Business Machines CorporationInventors: Wendy Belluomini, Andrew Martin, Chandler McDowell
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Publication number: 20050102345Abstract: A 4-to-2 carry save adder using limited switching dynamic logic (LSDL) to reduce power consumption while reducing the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a first LSDL circuit configured to output a sum bit. The carry save adder may further include a second LSDL circuit configured to output a carry bit. Both the first and second LSDL circuits use a carry generated in the current stage that was previously generated in the previous stage (next lower order bit position). Since the carry is generated in the current stage and not in the previous stage, the delay in outputting the sum and carry bits is reduced and hence the performance of carry save adders is improved. Further, since LSDL circuits were used in the carry save adder, power consumption was reduced while using a small amount of area.Type: ApplicationFiled: November 6, 2003Publication date: May 12, 2005Applicant: International Business Machines CorporationInventors: Wendy Belluomini, Ramyanshu Datta, Chandler McDowell, Robert Montoye, Hung Ngo
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Publication number: 20050102346Abstract: A 4-to-2 carry save adder with a reduction in the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a lower order full order coupled to a higher order full adder. The carry save adder may further include a logic unit coupled to the higher order full adder where the logic unit is configured to generate a carry bit to be inputted to the higher order full adder that normally would be generated from the carry save adder located in the previous stage. By generating this carry bit (carry-in bit) in the current stage and not in the previous stage, the delay of the carry-in bit inputted to the higher order full adder is reduced thereby reducing the delay of outputting the sum and carry bits by the higher order full adder.Type: ApplicationFiled: November 6, 2003Publication date: May 12, 2005Applicant: International Business Machines CorporationInventors: Wendy Belluomini, Ramyanshu Datta, Jente Kuang, Chandler McDowell, Robert Montoye, Hung Ngo
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Publication number: 20050080834Abstract: A multiplier circuit comprises a fused Booth encoder multiplexer which produces partial product bits, a tree which uses the partial product bits to generate partial products, and an adder which uses the partial products to generate intermediate sum and carry results for a multiplication operation. The fused Booth encoder multiplexer utilizes encoder-selector cells having a logic tree which carries out a Boolean function according to a Booth encoding and selection algorithm to produce one of the partial product bits at a dynamic node, and a latch connected to the dynamic node which maintains the value at an output node. The encoder-selector cells operate in parallel to produce the partial product bits generally simultaneously. A given one of the encoder-selector cells has a unique set of both multiplier operand inputs and multiplicand operand inputs, and produces a single partial product bit.Type: ApplicationFiled: September 30, 2003Publication date: April 14, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Wendy Belluomini, Hung Ngo, Jun Sawada
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Publication number: 20050071717Abstract: A method and system for manipulating data in a state holding elements array. Process data is moved through the state holding elements array by a process controller. A separate scan controller scans data out of the state holding elements array by scanning data out of a group of cascaded latches where there are insufficient extra state holding elements in the group to enable normal scan. A multiplicity of local scan clocks are utilized to shift selected amounts of data only when a next state holding element in the group has been made available by clearing the contents of that next state holding element. In this way, any given latch, for the purpose of scan, is not a dedicated master or slave latch, but can act as either. This invention also addresses a circuit for the creation of the multiplicity of local clocks from a conventional LSSD clock source.Type: ApplicationFiled: September 25, 2003Publication date: March 31, 2005Applicant: International Business Machines Corp.Inventors: Wendy Belluomini, Andrew Martin, Chandler McDowell, Robert Montoye
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Patent number: 6873188Abstract: Selector circuits and systems for single and multilevel selection within one clock cycle having a static switching factor on the output of a dynamic logic circuit. A logic device for single and multilevel selection having a dynamic logic circuit portion and a static logic circuit portion is implemented. In this way, an output logic state is maintained so long as the value of the Boolean operation being performed by the logic device does not change. Additionally, static logic elements may perform the inversions necessary to output both logic senses, mitigating the need to provide for dual-rail dynamic logic implementations. An asymmetric clock permits a concomitant decrease in the size of the precharge transistors thus ameliorating the area required by the logic element and obviating a need for keeper device.Type: GrantFiled: September 12, 2002Date of Patent: March 29, 2005Assignee: International Business Machines CorporationInventors: Wendy A. Belluomini, Robert K. Montoye, Hung C. Ngo
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Publication number: 20040051560Abstract: Selector circuits and systems for single and multilevel selection within one clock cycle having a static switching factor on the output of a dynamic logic circuit. A logic device for single and multilevel selection having a dynamic logic circuit portion and a static logic circuit portion is implemented. In this way, an output logic state is maintained so long as the value of the Boolean operation being performed by the logic device does not change. Additionally, static logic elements may perform the inversions necessary to output both logic senses, mitigating the need to provide for dual-rail dynamic logic implementations. An asymmetric clock permits a concomitant decrease in the size of the precharge transistors thus ameliorating the area required by the logic element and obviating a need for keeper device.Type: ApplicationFiled: September 12, 2002Publication date: March 18, 2004Applicant: International Business Machines CorporationInventors: Wendy A. Belluomini, Robert K. Montoye, Hung C. Ngo
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Patent number: 6690204Abstract: Circuits and systems for producing a static switching factor on the output lines of dynamic logic devices. A logic device having a plurality of dynamic logic circuits each performing a Boolean function on a plurality of inputs and generating an output on a dynamic node. The corresponding plurality of dynamic outputs are coupled to a static logic circuit which performs an additional Boolean function of the plurality of dynamic outputs. The static logic circuit operates to generate an output logic state that is maintained so long as the value of the Boolean operations being performed by the logic device do not change. Additionally, static logic elements may perform the inversions necessary to output both logic senses, mitigating the need to provide for dual-rail dynamic logic implementations. An asymmetric clock permits a concomitant decrease in the size of the precharge transistors, thus ameliorating the area required by the logic element.Type: GrantFiled: September 12, 2002Date of Patent: February 10, 2004Assignee: International Business Machines CorporationInventors: Wendy A. Belluomini, Robert K. Montoye, Hung C. Ngo