Abstract: A test region layout for testing shallow trench isolation gap fill characteristics is disclosed. Each test region further comprises at least one test pattern disposed in an interior portion of the test region. In a preferred embodiment, the test pattern is a square shape or, more preferably, two diametrically opposed “L” shapes which are discontinuous with respect to each other. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: A method for enhancing uniformity in the polishing profile of a substrate during chemical mechanical polishing. According to a first embodiment, the method is adapted for a rotary-type chemical mechanical polisher and includes dispensing the polishing slurry onto the rotating polishing pad of the CMP apparatus in a polishing area on the polishing pad that contacts the entire surface area of the substrate. This facilitates substantially equal polishing rates and a substantially uniform polishing profile from the center to the edge regions on the surface of the substrate. According to a second embodiment, the method of the present invention is adapted for a linear-type chemical mechanical polisher and includes increasing the number of nozzles that dispense the slurry onto the polishing pad across the diameter or width of the substrate.

Abstract: A novel embedded fastener apparatus and method for fastening components to the interior of a process chamber of a semiconductor fabrication apparatus. In one embodiment, an apparatus having a showerhead or gas distribution plate which is mounted to the interior of the process chamber using multiple fasteners which are embedded in respective fastener openings in the showerhead. In another embodiment, an apparatus having a showerhead which is mounted to the interior of the process chamber using multiple exterior fasteners which extend into the showerhead through the walls of the process chamber. Accordingly, the regions of the showerhead which surround the fasteners are physically separated from the interior of the process chamber.

Abstract: A plasma etching method for improving an etching profile including providing a substrate including an oxide containing insulating layer in a multilayer semiconductor device; providing a patterned photoresist layer exposing an uppermost layer of the substrate for anisotropically plasma etching a first opening; anisotropically plasma etching through a thickness of at least a portion of the substrate to form the first opening; blanket depositing an etching stop liner to cover at least a portion of the sidewalls of the first opening; patterning according to a photolithographic process for etching a second opening at least partially overlying and encompassing the first opening; and, anisotropically plasma etching through at least another portion of the thickness of the substrate including the first opening to form a second opening at least partially overlying a remaining portion of the first opening.

Abstract: A new method and sequence is provided for the polishing of the surface of a layer of metal containing copper. The invention provides for an improved method of residue removal. The invention improves the removal of slurry as part of the step of applying DIW by, during the step of applying DIW, raising the wafer carrier, thus allowing uninhibited removal of the slurry from the surface that is being polished.

Abstract: A SiOC layer and/or a SiC layer of an etch stop layer may be improved by altering the process used to form them. In a bi-layer structure, a SiOC layer and/or a SiC layer may be improved to provide better reliability. A silicon carbide (SiC) layer may be used to form a single-layer etch stop layer, while also acting as a glue layer to improve interface adhesion. Preferably, the SiC layer is formed in a reaction chamber having a flow of substantially pure trimetholsilane (3MS) streamed into and through the reaction chamber under a pressure of less than about 2 torr therein. Preferably, the reaction chamber is energized with high frequency RF power of about 100 watts or more. Preferably, the SiOC layer is formed in a reaction chamber having a flow of 3MS and CO2, and is energized with low frequency RF power of about 100 watts or more.

Abstract: An improved and new process, used for the elimination of copper line damage, copper defects, non-uniformity improvement, with low dishing and erosion, in damacene processing, is disclosed. This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the elimination of copper line damage for damascene processing, by depositing a multilayer interface material, consisting of a mechanically hard film and a soft film, over a low dielectric constant, interlevel metal dielectric (IMD), and subsequently chemical mechanical polishing (CMP) back the excess material to planarize the surface.

Abstract: A method and a system for integration of engineering change data are provided. A form generation module searches engineering change data from a database according to search conditions entered by a user via a terminal device and generates accordingly generates an electronic form to which the user modifies the engineering change data. A modification module modifies data of an associated engineering change order with the modified engineering change data. Then, a searching module searches associated engineering change data file from the database according to the search conditions entered by the user. By the above data integration method and system, all related engineering data may be changed in response to modification of any particular engineering data by the user, and associated engineering data can also be searched during the process of searching particular engineering change data.

Abstract: A new method and sequence is provided for the polishing of the surface of a layer of metal containing copper. One of the main problems that is conventionally encountered during the polishing of a copper surface is insufficient removal of the slurry and the therein contained residue of semiconductor materials. The invention therefore provides for an improved method of residue removal. Using the conventional step of applying DIW, the contact between the polishing pad and the surface that is being polished is constant and uninterrupted during the step of applying DIW. The invention improves the removal of slurry as part of the step of applying DIW by, during the step of applying DIW, raising the wafer carrier, thus allowing uninhibited removal of the slurry from the surface that is being polished.

Abstract: A method and a system for managing engineer-modified trial operation are provided, for use in an enterprise to perform automatic integration planning for engineer-modified related processes. By computer information management technology and network technology, an online trial operation procedure is executed for a confirmed engineer-modified project. This procedure involves material planning and uploading trial data to a quality control department after the trial is completed to produce a trial operation test report that is directed to associated departments. Compared to the prior art, the integration planning conducted by the proposed system allows employees of the enterprise to more easily access and manage data in real time, thereby improving operational efficiency of the enterprise.

Abstract: A plasma etching method for improving an etching profile including providing a substrate including an oxide containing insulating layer in a multilayer semiconductor device; providing a patterned photoresist layer exposing an uppermost layer of the substrate for anisotropically plasma etching a first opening; anisotropically plasma etching through a thickness of at least a portion of the substrate to form the first opening; blanket depositing an etching stop liner to cover at least a portion of the sidewalls of the first opening; patterning according to a photolithographic process for etching a second opening at least partially overlying and encompassing the first opening; and, anisotropically plasma etching through at least another portion of the thickness of the substrate including the first opening to form a second opening at least partially overlying a remaining portion of the first opening.

Abstract: A chemical mechanical polish (CMP) planarizing method for forming a chemical mechanical polish (CMP) planarized layer within a microelectronic fabrication. There is first provided a substrate. There is then formed over the substrate a chemical mechanical polish (CMP) substrate layer having an aperture formed therein. There is then formed upon the chemical mechanical polish (CMP) substrate layer and completely filling the aperture within the chemical mechanical polish (CMP) substrate layer a blanket chemical mechanical polish (CMP) planarizable layer. There is then chemical mechanical polish (CMP) planarized, while employing a chemical mechanical polish (CMP) planarizing method, the blanket chemical mechanical polish (CMP) planarizable layer to form within the aperture from the blanket chemical mechanical polish (CMP) planarizable layer a patterned chemical mechanical polish (CMP) planarized layer.

Abstract: Within a method for fabricating a microelectronic fabrication having formed therein a copper containing conductor layer passivated with a passivation layer, there is first: (1) pre-heated the copper containing conductor layer to a temperature of from about 300 to about 450 degrees centigrade for a time period of from about 30 to about 120 seconds to form a pre-heated copper containing conductor layer; and then (2) plasma treated the pre-heated copper containing conductor layer within a reducing plasma to form a plasma treated pre-heated copper containing conductor layer; prior to (3)forming upon the plasma treated pre-heated copper containing conductor layer the passivation layer. The foregoing process sequence provides for attenuated hillock defects within the plasma treated pre-heated copper containing conductor layer when forming the passivation layer thereupon.

Abstract: Disclosed is an automated staining apparatus including an arm (30) moveable in three dimensions, and a hollow tip head (70) located on the arm including integral reagent tip head (40), wash tip (41) and blow tip (42) for selectively dispensing gas and liquid onto microscope slides. Also disclosed are various sub-components of the apparatus that are specifically adapted to the processing of specimens on slides.

Abstract: Within a dual damascene method for forming a contiguous patterned conductor interconnect and patterned conductor stud layer within a corresponding trench contiguous with a corresponding via formed through a dielectric layer formed of a comparatively low dielectric constant dielectric material, the dielectric layer is, prior to dual damascene etching, formed of a patterned first dielectric layer having formed thereupon a blanket second dielectric layer. The patterned first dielectric layer is formed of a first dielectric material and the blanket second dielectric layer is formed of a second dielectric material, where each of the first dielectric material and the second dielectric material has a dielectric constant of less than about 4.0, but wherein the first dielectric material serves as an intrinsic etch stop when dual damascene etching the dielectric layer.

Abstract: Within a series of chemical mechanical polish (CMP) planarizing methods for forming a series of damascene structures within a series of microelectronic fabrications, there is employed at least one lateral offset width between: (1) a sidewall of a patterned dielectric layer and an edge of a substrate; (2) a sidewall of a patterned conductor layer and a sidewall of a patterned dielectric layer; and (3) a sidewall of a patterned second dielectric layer and a sidewall of a first dielectric layer. By employing the at least one lateral offset, there is provided the series of damascene structures with inhibited physical degradation of a patterned dielectric layer when forming within an aperture defined by the patterned dielectric layer a chemical mechanical polish (CMP) planarized patterned conductor layer.

Abstract: Within a series of chemical mechanical polish (CMP) planarizing methods for forming a series of damascene structures within a series of microelectronic fabrications, there is employed at least one lateral offset width between: (1) a sidewall of a patterned dielectric layer and an edge of a substrate; (2) a sidewall of a patterned conductor layer and a sidewall of a patterned dielectric layer; and (3) a sidewall of a patterned second dielectric layer and a sidewall of a first dielectric layer. By employing the at least one lateral offset, there is provided the series of damascene structures with inhibited physical degradation of a patterned dielectric layer when forming within an aperture defined by the patterned dielectric layer a chemical mechanical polish (CMP) planarized patterned conductor layer.

Abstract: A method of forming an organic low k layer, for use as an interlevel dielectric layer in semiconductor integrated circuits, has been developed. An organic low k layer, such as a poly arylene ether layer, with a dielectric constant between about 2.6 to 2.8, is applied on an underlying metal interconnect pattern. The moisture contained in the as applied, organic low k layer, or the moisture absorbed by the organic low k layer, due to exposure to the environment, is then reduced via a high density plasma treatment, performed in a nitrogen ambient. The reduction in moisture can be accomplished, even when the organic low k layer had been exposed to the environment for a period of time as great as three months. The dielectric constant, of the organic low k layer, remains unchanged, as a result of the high density plasma treatment.

Abstract: Chemical mechanical polishing (CMP) is known to cause dishing when the surface being planarized includes a wide trench partially filled with metal. This problem has been overcome by first filling the trench with a material whose polishing rate under CMP is similar to that of the metal in the trench. Spin-coating is used for this so that only the trench gets filled. After CMP, any residue of this material is removed, leaving behind a surface that has been planarized to the intended extent without the introduction of significant dishing and with minimum erosion of the metal.

Abstract: Within a method for removing from over a substrate a chemical mechanical polish (CMP) residue layer there is first provided a substrate. There is then formed over the substrate: (1) a chemical mechanical polish (CMP) substrate layer having an aperture formed therein; (2) a chemical mechanical polish (CMP) planarized patterned layer formed within the aperture within the chemical mechanical polish (CMP) substrate layer; and (3) a chemical mechanical polish (CMP) residue layer formed upon at least one of the chemical mechanical polish substrate layer and the chemical mechanical polish (CMP) planarized patterned layer, where at least one of the chemical mechanical polish (CMP) substrate layer and the chemical mechanical polish (CMP) planarized patterned layer has a first aqueous contact angle.