Abstract: An electronic component including a housing, a flexible battery and multiple first terminals is provided. The housing includes an outer surface and an inner surface opposite to the outer surface. At least a portion of the flexible battery is embedded in the housing. The multiple first terminals are disposed on the inner surface of the housing and electrically connected with the flexible battery. An electronic apparatus including the electronic component is also provided.

Abstract: Provided is a semiconductor device that includes a first transistor and a second transistor that are formed on the same substrate. The first transistor includes a first collector, a first base, and a first emitter. The first collector includes a first doped well disposed in the substrate. The first base includes a first doped layer disposed above the substrate and over the first doped well. The first emitter includes a doped element disposed over a portion of the first doped layer. The second transistor includes a second collector, a second base, and a second emitter. The second collector includes a doped portion of the substrate. The second base includes a second doped well disposed in the substrate and over the doped portion of the substrate. The second emitter includes a second doped layer disposed above the substrate and over the second doped well.

Abstract: A display having a first substrate and a second substrate parallel to each other, a cathode layer, a plurality of electroluminescences, a plurality of anodes, and a driving circuit is provided. The first substrate has a first surface. The second substrate has a second surface and a third surface opposite to each other, and the second surface faces the first surface. At least one of the first and the second substrates is transparent. The cathode layer disposed at the first surface has a plurality of tips. The plural electroluminescences are disposed at the second surface, and an interval is formed between the plural electroluminescences and the cathode layer. The positions of the plural anodes are at the third surface and correspond to the positions of plural electroluminescences on the second substrate. The driving circuit is disposed at the third surface and electrically connected to the plural anodes.

Abstract: An electronic device including a casing and a display module is provided. The casing has an opening. The display module is disposed in the casing and includes a backlight module and a display panel. The display panel is disposed on the backlight module and located between the backlight module and the opening. The display panel entirely covers the backlight module, and the periphery of the display panel is adjacent to the casing.

Abstract: An electronic device and an adjustment method thereof are provided. Generate an adjustment voltage according to a preset capacitance and a capacitance detected by a capacitive sensor coupled to both sides of a piezoelectric element, and generate a driving voltage to drive the piezoelectric element according to the adjustment voltage, so as to avoid depolarization of the piezoelectric element affecting the vibration strength of the vibration device.

Abstract: An organic light emitting display (OLED) including a transparent substrate, a mirror layer, a transparent insulating layer, and an organic light emitting displaying layer is provided. The mirror layer is disposed on the transparent substrate and has a plurality of openings. The transparent insulating layer is disposed on the transparent substrate and covers the mirror layer. The organic light emitting displaying layer is disposed on the transparent insulating layer and has a plurality of pixel regions. The openings are aligned to the pixel regions respectively. In addition, a method for manufacturing the OLED is also provided.

Abstract: A display having a first substrate and a second substrate parallel to each other, a cathode layer, a plurality of electroluminescences, a plurality of anodes, and a driving circuit is provided. The first substrate has a first surface. The second substrate has a second surface and a third surface opposite to each other, and the second surface faces the first surface. At least one of the first and the second substrates is transparent. The cathode layer disposed at the first surface has a plurality of tips. The plural electroluminescences are disposed at the second surface, and an interval is formed between the plural electroluminescences and the cathode layer. The positions of the plural anodes are at the third surface and correspond to the positions of plural electroluminescences on the second substrate. The driving circuit is disposed at the third surface and electrically connected to the plural anodes.

Abstract: A composite semiconductor structure and method of forming the same are provided. The composite semiconductor structure includes a first silicon-containing compound layer comprising an element selected from the group consisting essentially of germanium and carbon; a silicon layer on the first silicon-containing compound layer, wherein the silicon layer comprises substantially pure silicon; and a second silicon-containing compound layer comprising the element on the silicon layer. The first and the second silicon-containing compound layers have substantially lower silicon concentrations than the silicon layer. The composite semiconductor structure may be formed as source/drain regions of metal-oxide-semiconductor (MOS) devices.

Abstract: An exemplary structure for a gate structure of a field effect transistor comprises a gate electrode; a gate insulator under the gate electrode having footing regions on opposing sides of the gate electrode; and a sealing layer on sidewalls of the gate structure, wherein a thickness of lower portion of the sealing layer overlying the footing regions is less than a thickness of upper portion of the sealing layer on sidewalls of the gate electrode, whereby the field effect transistor made has almost no recess in the substrate surface.

Abstract: A camera module includes a circuit board; a lens electrically connected to the circuit board; a adjusting base disposed on the circuit board and having at least two through-hole disposed adjacent to opposite sides of the lens; at least two fixed posts; at least two adjusting screw respectively passing through the through-holes of the adjusting base so as to be secured in the fixed posts; and at least two springs respectively encircling the adjusting screws, wherein two ends of each spring are positioned against the adjusting base and one of the fixed post respectively.

Abstract: Provided is a semiconductor device that includes a first transistor and a second transistor that are formed on the same substrate. The first transistor includes a first collector, a first base, and a first emitter. The first collector includes a first doped well disposed in the substrate. The first base includes a first doped layer disposed above the substrate and over the first doped well. The first emitter includes a doped element disposed over a portion of the first doped layer. The second transistor includes a second collector, a second base, and a second emitter. The second collector includes a doped portion of the substrate. The second base includes a second doped well disposed in the substrate and over the doped portion of the substrate. The second emitter includes a second doped layer disposed above the substrate and over the second doped well.

Abstract: An exemplary structure for a gate structure of a field effect transistor comprises a gate electrode; a gate insulator under the gate electrode having footing regions on opposing sides of the gate electrode; and a sealing layer on sidewalls of the gate structure, wherein a thickness of lower portion of the sealing layer overlying the footing regions is less than a thickness of upper portion of the sealing layer on sidewalls of the gate electrode, whereby the field effect transistor made has almost no recess in the substrate surface.

Abstract: Provided is a semiconductor device including a substrate. A gate formed on the substrate. The gate includes a sidewall. A spacer formed on the substrate and adjacent the sidewall of the gate. The spacer has a substantially triangular geometry. A contact etch stop layer (CESL) is formed on the first gate and the first spacer. The thickness of the CESL to the width of the first spacer is between approximately 0.625 and 16.

Abstract: Provided is a semiconductor device including a substrate. A gate formed on the substrate. The gate includes a sidewall. A spacer formed on the substrate and adjacent the sidewall of the gate. The spacer has a substantially triangular geometry. A contact etch stop layer (CESL) is formed on the first gate and the first spacer. The thickness of the CESL to the width of the first spacer is between approximately 0.625 and 16.

Abstract: A composite semiconductor structure and method of forming the same are provided. The composite semiconductor structure includes a first silicon-containing compound layer comprising an element selected from the group consisting essentially of germanium and carbon; a silicon layer on the first silicon-containing compound layer, wherein the silicon layer comprises substantially pure silicon; and a second silicon-containing compound layer comprising the element on the silicon layer. The first and the second silicon-containing compound layers have substantially lower silicon concentrations than the silicon layer. The composite semiconductor structure may be formed as source/drain regions of metal-oxide-semiconductor (MOS) devices.

Abstract: A method for fabricating a semiconductor device is disclosed. The method includes providing a first chamber and a second chamber. The first chamber and the second chamber are connected by a pressure differential unit, for depositing a metallic film over a substrate in the first chamber, transferring the substrate to the second chamber via the pressure differential unit without exposing the substrate to the ambient environment, and depositing a silicon-containing film on the metallic film in the second chamber.

Abstract: A SiOC layer and/or a SiC layer of an etch stop layer may be improved by altering the process used to form them. In a bi-layer structure, a SiOC layer and/or a SiC layer may be improved to provide better reliability. A silicon carbide (SiC) layer may be used to form a single-layer etch stop layer, while also acting as a glue layer to improve interface adhesion. Preferably, the SiC layer is formed in a reaction chamber having a flow of substantially pure trimetholsilane (3MS) streamed into and through the reaction chamber under a pressure of less than about 2 torr therein. Preferably, the reaction chamber is energized with high frequency RF power of about 100 watts or more. Preferably, the SiOC layer is formed in a reaction chamber having a flow of 3MS and CO2, and is energized with low frequency RF power of about 100 watts or more.

Abstract: A metal-oxide-semiconductor (MOS) transistor having a gate electrode comprising a metal oxynitride and a method of forming the same are provided. The metal oxynitride preferably comprises molybdenum oxynitride and/or iridium oxynitride. The gate electrode may further comprise carbon and/or silicon. The gate electrode is preferably formed in a chamber containing nitrogen, oxygen and a carbon-containing gas. The gate electrode of the MOS transistor has a high work function and a low equivalent oxide thickness.

Abstract: A semiconductor substrate has a first copper layer, on which an etch stop layer and a dielectric layer are successively formed. A second copper layer penetrates the dielectric layer and the etch stop layer to electrically connect to the first metal layer. The etch stop layer has a dielectric constant smaller than 3.5, and the dielectric layer has a dielectric constant smaller than 3.0.

Abstract: A method of forming a SiCOH etch stop layer in a copper damascene process is described. A substrate with an exposed metal layer is treated with H2 or NH3 plasma to remove metal oxides. Trimethylsilane is flowed into a chamber with no RF power at about 350° C. to form at least a monolayer on the exposed metal layer. The SiCOH layer is formed by a PECVD process including trimethylsilane and CO2 source gases. Optionally, a composite SiCOH layer comprised of a low compressive stress layer on a high compressive stress layer is formed on the substrate. A conventional damascene sequence is then used to form a second metal layer on the exposed metal layer. Via Rc stability is improved and a lower leakage current is achieved with the trimethylsilane passivation layer. A composite SiCOH etch stop layer provides improved stress migration resistance compared to a single low stress SiCOH layer.