Abstract: A piezoresistive microphone includes a substrate, an insulating layer, and a polysilicon layer. A first pattern is disposed within the polysilicon layer. The first pattern includes numerous first opening. A second pattern is disposed within the polysilicon layer. The second pattern includes numerous second openings. The first pattern surrounds the second pattern. Each first opening and each second opening are staggered. A first resistor is disposed in the polysilicon and between the first pattern and the second pattern. The first resistor is composed of numerous first heavily doped regions and numerous first lightly doped regions. The first heavily doped regions and the first lightly doped regions are disposed in series. The first heavily doped region and the first lightly doped region are disposed alternately. A cavity is disposed in the insulating layer and the substrate.

Abstract: A micro-electro-mechanical (MEMS) structure and a method for forming the same are disclosed. The MEMS structure includes a sacrificial layer, a lower dielectric film, an upper dielectric film, a plurality of through holes and a protective film. The sacrificial layer comprises an opening. The lower dielectric film is on the sacrificial layer. The upper dielectric film is on the lower dielectric film. The plurality of through holes passes through the lower dielectric film and the upper dielectric film. The protective film covers side walls of the upper dielectric film and the lower dielectric film and a film interface between the lower dielectric film and the upper dielectric film.

Abstract: A semiconductor sensor, comprising a gas-sensing device and an integrated circuit electrically connected to the gas-sensing device, is provided. The gas-sensing device includes a substrate having a sensing area and an interconnection area in the vicinity of the sensing area, an inter-metal dielectric (IMD) layer formed above the substrate in the sensing area and in the interconnection area, and an interconnect structure formed in the interconnection area. The interconnect structure includes a tungsten layer buried in the IMD layer, wherein part of a top surface of the tungsten layer is exposed by at least a via. The interconnect structure further includes a platinum layer formed in said at least the via, wherein the platinum (Pt) layer directly contacts the top surface of the tungsten layer.

Abstract: A piezoresistive microphone includes a substrate, an insulating layer, and a polysilicon layer. A first pattern is disposed within the polysilicon layer. The first pattern includes numerous first opening. A second pattern is disposed within the polysilicon layer. The second pattern includes numerous second openings. The first pattern surrounds the second pattern. Each first opening and each second opening are staggered. A first resistor is disposed in the polysilicon and between the first pattern and the second pattern. The first resistor is composed of numerous first heavily doped regions and numerous first lightly doped regions. The first heavily doped regions and the first lightly doped regions are disposed in series. The first heavily doped region and the first lightly doped region are disposed alternately. A cavity is disposed in the insulating layer and the substrate.

Abstract: A method of fabricating a MEMS structure includes providing a substrate comprising a logic element region and a MEMS region. Next, a logic element is formed within the logic element region. A nitrogen-containing material layer is formed to cover the logic element region and the MEMS region conformally. Then, part of the nitrogen-containing material layer within the MEMS region is removed to form at least one shrinking region. Subsequently, a dielectric layer is formed to cover the logic element region and MEMS region, and the dielectric layer fills in the shrinking region. After that, the dielectric layer is etched to form at least one releasing hole, wherein the shrinking region surrounds the releasing hole. Finally, the substrate is etched to form a chamber.

Abstract: A method of fabricating a MEMS structure includes providing a substrate comprising a logic element region and a MEMS region. Next, a logic element is formed within the logic element region. A nitrogen-containing material layer is formed to cover the logic element region and the MEMS region conformally. Then, part of the nitrogen-containing material layer within the MEMS region is removed to form at least one shrinking region. Subsequently, a dielectric layer is formed to cover the logic element region and MEMS region, and the dielectric layer fills in the shrinking region. After that, the dielectric layer is etched to form at least one releasing hole, wherein the shrinking region surrounds the releasing hole. Finally, the substrate is etched to form a chamber.

Abstract: A micro-electro-mechanical (MEMS) structure and a method for forming the same are disclosed. The MEMS structure includes a sacrificial layer, a lower dielectric film, an upper dielectric film, a plurality of through holes and a protective film. The sacrificial layer comprises an opening. The lower dielectric film is on the sacrificial layer. The upper dielectric film is on the lower dielectric film. The plurality of through holes passes through the lower dielectric film and the upper dielectric film. The protective film covers side walls of the upper dielectric film and the lower dielectric film and a film interface between the lower dielectric film and the upper dielectric film.

Abstract: A method of fabricating a MEMS structure includes providing a substrate comprising a logic element region and a MEMS region. Next, a logic element is formed within the logic element region. A nitrogen-containing material layer is formed to cover the logic element region and the MEMS region conformally. Then, part of the nitrogen-containing material layer within the MEMS region is removed to form at least one shrinking region. Subsequently, a dielectric layer is formed to cover the logic element region and MEMS region, and the dielectric layer fills in the shrinking region. After that, the dielectric layer is etched to form at least one releasing hole, wherein the shrinking region surrounds the releasing hole. Finally, the substrate is etched to form a chamber.

Abstract: Provided herein is a semiconductor device is provided. The semiconductor device includes a substrate including a MEMS region and a connection region thereon; a dielectric layer disposed on the substrate in the connection region; a poly-silicon layer disposed on the dielectric layer, wherein the poly-silicon layer serves as an etch-stop layer; a connection pad disposed on the poly-silicon layer; and a passivation layer covering the dielectric layer, wherein the passivation layer includes an opening that exposes the connection pad and a transition region between the connection pad and the passivation layer.

Abstract: A method of fabricating a shuttle wafer is provided. First, a wafer including a number of shots is provided. Each of the shots includes a number of dies. A material layer is then formed on the wafer. After that, a shuttle mask having a number of IC designs is provided. A first IC design corresponds to a first die of each of the shots. A portion of the IC designs on the shuttle mask is covered for exposing the first IC design. Thereafter, the first IC designs of the shuttle mask are transferred onto the material layer, so as to form at least an effective IC pattern on the first die of each of the shots and to form an ineffective IC pattern on each of the other dies of each of the shots.

Abstract: A method for removing extraneous matters from a stainless device is provided. The method includes the steps of (a) providing a container for holding a fluorine-containing neutral solution therein, (b) immersing said stainless device in said fluorine-containing neutral solution to remove said extraneous matters from said stainless device, and (c) heating and swirling said fluorine-containing solution. The fluorine-containing neutral solution is made from neutralizing hydrofluoric acid (HF) with ammonium hydroxide (NH4OH), neutralizing hydrofluoric acid (HF) with ammonium fluoride (NH4F), or dissolving ammonium acid fluoride (NH4F) in a deionized water (DIW).

Abstract: An integrated circuit (IC) fabrication method is provided for fabricating a conductive plug, such as a contact plug or a via plug, with a low junction resistance in an integrated circuit. This method is characterized by the inclusion of a preliminary doping process to form a doped region in the exposed area through the contact opening or via opening. By conventional method, the exposed area would be formed with an undesired oxide layer or laid with undesired reactant remnants after the etching process for forming the contact opening or via opening. When being subjected to a high temperature during the subsequent deposition process, the dopant atoms in the doped region diffuse into these undesired insulative matters, thereby reducing the junction resistance of the resulting contact or via plug.

Abstract: A method of fabricating a coronary-type capacitor in integrated circuit is provided, which method helps increase the capacitance of the capacitor by forming the electrode of the capacitor with a coronary-like shape that is relatively large in surface area. In this method, a stacked structure of doped polysilicon layers and HSG polysilcon layers are formed in an alternating manner, which is then selectively removed to form a void portion. A heat-treatment process is then performed on the wafer at a temperature of about 600-700° C. to cause the impurity ions in the doped polysilicon layers to be activated and evenly diffused over the inside of the doped polysilicon layers. Finally, a selective etching process is performed with an etchant that can react with polysilicon at a faster etching rate than with HSG polysilcon so as to cause the sidewalls of the doped polysilicon layers to be more recessed than the sidewalls of the HSG polysilcon layers.

Abstract: An apparatus and a method of forming a thick polysilicon layer are provided. An additional pipeline is introduced into a chamber that is used for depositing polysilicon layers. A thin silicon dioxide film is formed using oxygen after forming a first doped polysilicon layer with a constant thickness. Then a second doped polysilicon layer with a constant thickness is deposited on the thin silicon dioxide layer. The steps described above are repeated until a desired thickness is attained.

Abstract: The method of the invention starts with forming a mask on a blank wafer, wherein the mask contains a number of openings that expose a portion of the wafer. By performing a wet oxidation process, field oxide is formed on the exposed surface of the wafer. The wafer surface is then become ragged after the mask and the field oxide are removed. In order to further increase the surface area of a dummy wafer, an etching process is performed on the ragged surface after a hemispherical grained layer is formed on the ragged surface.

Abstract: A method for fabricating a field effect transistor (FET) with a T-like gate structure includes forming a silicon nitride layer over a silicon substrate and patterning it to form an opening that exposes the substrate. A dielectric layer is formed on a lower portion of each side-wall of the opening so that the opening has a T-like free space. A doped polysilicon layer fills the T-like free space through only one deposition. After performing a planarization on the doped polysilicon layer, a titanium metal layer is formed over the substrate. A self-aligned titanium silicide is formed over the substrate other than the dielectric layer surface through a rapid thermal process (RTP). A selective etching process is performed to remove the remaining titanium metal layer. After removing the dielectric layer a RTP is performed again to reform the crystal structure of the titanium silicide layer so as to reduce its resistance. A T-like gate structure is formed.

Abstract: A method for fabricating a capacitor including a storage capacitor of a dynamic random access memory (DRAM) starts with forming a dielectric layer and then a mask on a provided substrate, wherein the provided substrate contains a pre-formed field effect transistor (FET). By patterning the dielectric layer, a contact window is formed to expose the source/drain regions on the provided substrate. Then, a conducting layer is formed to cover the mask and fill the contact window, wherein the conducting layer is electrically connected to the source/drain region. A hemispherical-grained silicon (HSG) layer is formed on the conducting layer, wherein the silicon grains are respectively surrounded by spacers formed in a follow-up process. The HSG layer and a portion of the conducting layer are removed by performing an anisotropic etching process that uses the spacers as masks. The remains of the conducting layer, a multi-micro-cylinder structure, serves as the storage electrode of a capacitor.