Patents by Inventor Wenhao Li
Wenhao Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250116001Abstract: A semiconductor processing chamber may include a pedestal configured to support a substrate during a plasma-enhanced chemical-vapor deposition (PECVD) process that forms a film on a surface of the substrate. The chamber may also include one or more internal meshes embedded in the pedestal. The one or more internal meshes may be configured to deliver radio-frequency (RF) power to a plasma in the semiconductor processing chamber during the PECVD process. An outer diameter of the one or more internal meshes may be less that a diameter of the substrate. The chamber may further include an RF source configured to deliver the RF power to the one more internal meshes. This configuration may reduce arcing within the processing chamber.Type: ApplicationFiled: October 6, 2023Publication date: April 10, 2025Applicant: Applied Materials, Inc.Inventors: Allison Yau, Manoj Kumar Jana, Wen-Shan Lin, Zhiling Dun, Xinhai Han, Deenesh Padhi, Jian Li, Yuanchang Chen, Wenhao Zhang, Edward P. Hammond, Alexander V. Garachtchenko, Ganesh Balasubramanian, Juan Carlos Rocha-Alvarez, Sathya Ganta
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Publication number: 20250112186Abstract: A surface of at least one of an integrated circuit (IC) die structure or a substrate structure to which the IC die structure is to be bonded include a biphilic region suitable for liquid droplet confinement and droplet-based fine alignment of the IC die structure to the substrate structure. A biphilic region may include an inner region surrounded by bonding regions, or between an adjacent pair of bonding regions. The inner region may improve fine alignment, particularly if there is a significant amount of tilt between a bonding surface of the IC die structure and a bonding surface of the substrate structure during placement. The inner region may, for example, facilitate the confinement of two or more droplets on the bonding regions. Inner or outer regions of a biphilic structure may be segmented or contiguous and intersecting IC die edges may also be non-orthogonal.Type: ApplicationFiled: September 28, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Feras Eid, Adel Elsherbini, Thomas Sounart, Kimin Jun, Wenhao Li
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Publication number: 20250112173Abstract: A surface of an integrated circuit (IC) die structure and a substrate to which the IC die structure is to be bonded include biphilic regions suitable for liquid droplet formation and droplet-based fine alignment of the IC die structure to the substrate. To ensure warpage of the IC die structure does not interfere with droplet-based fine alignment process, an IC die structure of greater thickness is aligned to the substrate and thickness of the IC die structure subsequently reduced. In some embodiments, a back side of the IC die structure is polished back post attachment. In some alternative embodiments, the IC die structure includes sacrificial die-level carrier is removed after fine alignment and/or bonding.Type: ApplicationFiled: September 28, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Kimin Jun, Feras Eid, Adel Elsherbini, Thomas Sounart, Yi Shi, Wenhao Li
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Publication number: 20250112181Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. An integrated circuit (IC) die and a surface of a substrate each include hybrid bonding regions surrounded by hydrophobic structures. The hydrophobic structures include non-vertical inward sloping sidewalls or similar features to contain a liquid droplet that is applied to the die or substrate hybrid bonding region. After the hybrid bonding regions are brought together, capillary forces cause the die to self-align, and a hybrid bond is formed by evaporating the liquid and subsequent anneal. IC structures including the IC die and portions of the substrate are segmented and assembled.Type: ApplicationFiled: September 28, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Feras Eid, Yi Shi, Kimin Jun, Adel Elsherbini, Thomas Sounart, Wenhao Li, Xavier Brun
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Publication number: 20250112177Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. An integrated circuit (IC) die backside surface and a surface of a structural substrate each include bonding regions surrounded by hydrophobic structures. A liquid droplet is applied to the die or structural substrate bonding region and the die is placed on the bonding region of the structural substrate. Capillary forces cause the die to self-align to the bonding region, and a bond is formed by evaporating the liquid and subsequent anneal. A hybrid bond is then formed between the opposing active surface of the die and a base substrate using wafer-to-wafer bonding. IC structures including the IC die and portions of the structural substrate and base substrate are segmented from the bonded wafers and assembled.Type: ApplicationFiled: September 28, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Feras Eid, Thomas Sounart, Yi Shi, Michael Baker, Adel Elsherbini, Kimin Jun, Xavier Brun, Wenhao Li
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Publication number: 20250109221Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. One or both of an integrated circuit (IC) die hybrid bonding region and a base substrate hybrid bonding region surrounded by hydrophobic structures that include a cross-linked material. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. A hybrid bond is formed by evaporating the droplet and a subsequent anneal. The cross-linked material hydrophobic structures contain the liquid droplet for alignment and are resistant to plasma treatment prior to bonding.Type: ApplicationFiled: September 28, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Wenhao Li, Veronica Strong, Feras Eid, Bhaskar Jyoti Krishnatreya
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Publication number: 20250111013Abstract: Provided are an information generation method and apparatus, and an electronic device.Type: ApplicationFiled: January 3, 2023Publication date: April 3, 2025Inventors: Xiaoming GAO, Qin LIU, Huihong LI, Fang CHEN, Shidi LIU, Yi YAN, Cong MAI, Jinming ZENG, Yunzhi LIU, Wenhao TAN, Guangwen CAI, Huiying DENG, Xiaoming XU, Yunbin SU, Xueming JIANG, Liyou ZHANG, Mingyi GUO, Jiechao LIAO, Xuehao LI
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Publication number: 20250112155Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. One or both of an integrated circuit (IC) die hybrid bonding region and a base substrate hybrid bonding region are surrounded by a protective layer and hydrophobic structures on the protective layer. The protective layer is formed prior to pre-bond processing to protect the hybrid bonding region during plasma activation, clean test, high temperature processing, or the like. Immediately prior to bonding, the hydrophobic structures are selectively applied to the protective layer. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. A hybrid bond is formed by evaporating the droplet and a subsequent anneal. The hydrophobic structures contain the liquid droplet for alignment during bonding.Type: ApplicationFiled: September 28, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Kimin Jun, Scott Clendenning, Feras Eid, Robert Jordan, Wenhao Li, Jiun-Ruey Chen, Tayseer Mahdi, Carlos Felipe Bedoya Arroyave, Shashi Bhushan Sinha, Anandi Roy, Tristan Tronic, Dominique Adams, William Brezinski, Richard Vreeland, Thomas Sounart, Brian Barley, Jeffery Bielefeld
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Publication number: 20250112199Abstract: Hybrid bonded multi-level die stacks, related apparatuses, systems, and methods of fabrication are disclosed. First-level integrated circuit (IC) dies and a base substrate each include hybrid bonding regions surrounded by hydrophobic structures. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. A hybrid bond is formed by evaporating the droplet followed by anneal. Hybrid bonding regions of second-level IC dies are similarly bonded to hybrid bonding regions on backsides of the first-level IC dies. This is repeated for any number of subsequent levels of IC dies. IC structures including the bonded IC dies and portions of the base substrate are segmented and assembled.Type: ApplicationFiled: September 28, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Thomas Sounart, Feras Eid, Adel Elsherbini, Yi Shi, Michael Baker, Kimin Jun, Wenhao Li
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Publication number: 20250082115Abstract: A child carrier includes: a seat portion; a buckle movably provided on the seat portion; a backrest portion connected to the seat portion and extending upward, the backrest portion having a plurality of adjustment holes formed therein from bottom to top; and a shoulder strap having a fixed end and a free end, the fixed end being fixed on a rear side of the backrest portion, the free end passing through one of the plurality of adjustment holes and being removably connected to the seat portion.Type: ApplicationFiled: November 27, 2024Publication date: March 13, 2025Inventors: Bo WU, Meifeng FAN, Wenhao LI
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Publication number: 20250079300Abstract: Magnetic inductors for microelectronics packages are provided. Magnetic inductive structures include a magnetic region, a magnetic region base region, and a conductive region that forms a channel within the magnetic region. The magnetic region has a different chemical composition than the base region. Additional structures are provided in which the magnetic region is recessed into a package substrate core. Further inductor structures are provided in which the conductive region includes through-core vias and the conductive region at least partially encircles a portion of a package substrate core. Additionally, methods of manufacture are provided for semiconductor packages that include magnetic inductors.Type: ApplicationFiled: August 30, 2023Publication date: March 6, 2025Inventors: Aleksandar ALEKSOV, Neelam PRABHU GAUNKAR, Henning BRAUNISCH, Wenhao LI, Feras EID, Georgios C. DOGIAMIS
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Patent number: 12241739Abstract: A bidirectional Littrow two-degree-of-freedom grating interference measurement device based on double gratings includes a transmission two-dimensional grating and a reflection two-dimensional grating. A dual-frequency laser emitted by a light source passes through the transmission two-dimensional grating with a specific grating pitch to form four beams in X direction and Y direction, the four beams are incident on the reflection two-dimensional grating at a Littrow angle, and the four beams diffracted by the reflection two-dimensional grating return to the transmission two-dimensional grating in an incidence direction along the same path; different orders of transmission light of the four beams of light in different directions may form stable interference signals carrying displacement information, and the stable interference signals are received by a detector.Type: GrantFiled: September 25, 2024Date of Patent: March 4, 2025Assignee: Changchun Institute of Optics, Fine Mechanics and Physics, Chinese Academy of SciencesInventors: Wenhao Li, Wenyuan Zhou, Zhaowu Liu, Yujia Sun, Lin Liu
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Publication number: 20250068123Abstract: A method and a device for compensating a surface error of a holographic grating substrate based on scanning and exposure technology relates to a technical field of grating development. The method and the device adopt surface error compensation technology based on phase modulation of interference fringes of a scanning beam interference lithography system. The method and the device solve a poor grating diffraction wavefront quality caused by a surface processing error in a field of holographic grating research and improves full-aperture diffraction wavefront quality of a grating.Type: ApplicationFiled: August 22, 2024Publication date: February 27, 2025Inventors: HESHIG BAYAN, SHAN JIANG, YUBO LI, ZHAOWU LIU, WEI WANG, WENHAO LI, SHUO LI, YANXIU JIANG
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Patent number: 12236066Abstract: An electronic device such as a voice-controlled speaker may have an array of strain gauges and light-emitting diodes. The light-emitting diodes may be configured to display dynamically adjustable button icons overlapping the strain gauges. Force measurements from the strain gauges may be used to adjust speaker output and other device operations.Type: GrantFiled: July 18, 2023Date of Patent: February 25, 2025Assignee: Apple Inc.Inventors: Zhengyu Li, Ming Gao, Wenhao Wang, Yuanzhen Fan
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Patent number: 12236010Abstract: Provided is a wearable display device. The wearable display device includes a display panel, comprising a display region and a peripheral region surrounding the display region; a plurality of light-emitting elements, configured to emit light to be irradiated to eyes of a user; a lens assembly, disposed on a light-exiting side of the display panel, the lens assembly comprising a lens mount and a lens within the lens mount, a light transmittance of the lens mount being greater than a threshold; and a plurality of photoelectric sensor assemblies in the peripheral region.Type: GrantFiled: May 27, 2021Date of Patent: February 25, 2025Assignee: BOE Technologies Group Co., Ltd.Inventors: Yapeng Li, Xuan Feng, Lei Wang, Ping Zhang, Wenhao Tian, Yunke Qin, Yangbing Li, Chengfu Xu
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Patent number: 12231093Abstract: A device, method, and system for signal distortion pre-correction, and a composite system are disclosed. The device-includes: a signal distortion correction network module, a correction parameter trainer, a data collection module connected to an external power amplifier module, and a first conversion module. The data collection module is configured to perform time-division collection on output signals of channels of the power amplifier module and output analog feedback signals to the first conversion module. The first conversion module is configured to convert the analog feedback signals into digital feedback signals. The correction parameter trainer is configured to determine a correction parameter according to the digital feedback signals and a forward signal inputted. The signal distortion correction network module is configured to correct the forward signal based on the correction parameter and output a pre-corrected signal.Type: GrantFiled: December 31, 2019Date of Patent: February 18, 2025Assignee: ZTE CORPORATIONInventors: Yunhua Li, Zheyuan Zhang, Wenhao Du, Dongfang Ning, Zuofeng Zhang, Zhengjian Dai
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Publication number: 20250053279Abstract: The embodiments of the disclosure provide a method, apparatus, device and storage medium for presenting information, which relate to the technical field of computers. The method includes: obtaining object search information, in response to the object search information being object category information, determining a target object category corresponding to the object search information, and presenting object information of a plurality of target objects corresponding to the target object category in a search result presentation page; where all the plurality of target objects are different, and object information of a target object includes object attribute information and image resource information of the target object. By employing the above technical solution, when the user is searching the object category, object information of a plurality of target objects different from each other corresponding to the target object category is presented in the search result page.Type: ApplicationFiled: August 9, 2024Publication date: February 13, 2025Inventors: Jing LIN, Duanliang ZHOU, Long RU, Chao WU, Conghai YAO, Yelun LIU, Bin QIAN, Siyi YE, Jie WANG, Wenhao LI, Wenjing LIU, Shengan CAI, Tingting YANG, Yiwei WANG, Junjun YAO, Yifei QIU, Ju YANG, Yunfei SONG, Chuan ZHAO, Xianhui WEI, Xiaofeng WANG, Jianwen WU, Meng CHEN, Mang WANG, Peng HE, Kaijian LIU, Liangpeng XU, Yuhang LIU, Xiang XIAO, Runyu CHEN, Da LEI, Xiangnan LUO, Zheng PENG, Shaolong CHEN, Binghua XU, Hongtao XUE, Guorong ZHU, Qinglin XU, Pingping HUANG, Hongtao HU
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Publication number: 20250047921Abstract: In some embodiments, a method generates a reward function for an adaptive bitrate function that is based on a bandwidth and profiles in a profile ladder for a current segment of content. The reward function indicates a first profile should be selected for the current segment. The method performs a quality change analysis to select a second profile from the profile. The quality change analysis analyzes a quality change that is based on a previously selected profile from a prior segment and profiles in the profile ladder. The second profile is requested from the profile ladder for the current segment.Type: ApplicationFiled: August 16, 2023Publication date: February 6, 2025Applicant: Beijing YoJaJa Software Technology Development Co., Ltd.Inventors: Tongyu Dai, Si Chen, Wenhao Zhang, Boya Lai, Chao Li, Weiran Shi
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Patent number: D1066731Type: GrantFiled: July 3, 2023Date of Patent: March 11, 2025Assignee: MGI Tech Co., Ltd.Inventors: Yanning Zhu, Shaohua Li, Zhicheng Li, Wenhao Wu, Chunyu Geng, Jing Li
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Patent number: D1067331Type: GrantFiled: June 5, 2024Date of Patent: March 18, 2025Assignee: Dongguan Boyueda Technology Co., Ltd.Inventor: Wenhao Li