Patents by Inventor Wenmei Li
Wenmei Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8487373Abstract: Methods for forming a memory cell are disclosed. A method includes forming a source-drain structure in a semiconductor substrate where the source-drain structure includes a rounded top surface and sidewall surfaces. An oxide layer is formed on the top and sidewall surfaces of the source-drain structure. The thickness of the portion of the oxide layer that is formed on the top surface of the source-drain structure is greater than the thickness of the portion of the oxide layer that is formed on the sidewall surfaces of the source-drain structure.Type: GrantFiled: April 29, 2009Date of Patent: July 16, 2013Assignee: Spanion LLCInventors: Shenqing Fang, Gang Xue, Wenmei Li, Inkuk Kang
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Patent number: 8441041Abstract: An integrated circuit memory device, in one embodiment, includes a substrate and first and second inter-level dielectric layers successively disposed on the substrate. One or more contacts in the peripheral extend through the first inter-level dielectric layer to respective components. One or more vias and a plurality of dummy vias extend through the second inter-level dielectric layer in the peripheral area. Each of the one or more peripheral vias extend to a respective peripheral contact. The peripheral dummy vias are located proximate the peripheral vias.Type: GrantFiled: November 10, 2010Date of Patent: May 14, 2013Assignee: Spansion LLCInventors: Shenqing Fang, Wenmei Li
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Patent number: 8367493Abstract: A method of manufacturing a non-volatile memory device includes forming a number of memory cells. The method also includes depositing a first dielectric layer over the memory cells, where the first dielectric layer is a conformal layer having a substantially uniform thickness. The method further includes depositing a second dielectric layer over the first dielectric layer. Together, the first and second dielectric layers form an interlayer dielectric without voids.Type: GrantFiled: April 20, 2005Date of Patent: February 5, 2013Assignees: Spansion LLC, Advanced Micro Devices, Inc.Inventors: Minh Van Ngo, Hirokazu Tokuno, Angela T. Hui, Wenmei Li, Hsiao-Han Thio
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Publication number: 20120262716Abstract: A method and system for intelligently identifying and reading an immunochromatographic strip is disclosed.Type: ApplicationFiled: August 17, 2010Publication date: October 18, 2012Applicant: GUANGZHOU WONDFO BIOTECH. CO., LTD.Inventors: Jihua Wang, Wenmei Li
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Publication number: 20120056260Abstract: A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.Type: ApplicationFiled: November 10, 2011Publication date: March 8, 2012Applicant: Spansion LLCInventors: Shenqing Fang, Chun Chen, Wenmei Li, Inkuk Kang, Gang Xue, Hyesook Hong
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Patent number: 8076199Abstract: A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.Type: GrantFiled: February 13, 2009Date of Patent: December 13, 2011Assignee: Spansion LLCInventors: Shenqing Fang, Chun Chen, Wenmei Li, Inkuk Kang, Gang Xue, Hyesook Hong
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Patent number: 8022468Abstract: A memory device may include a substrate, a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may also include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer. The memory device may further include an interlayer dielectric formed over the control gate and the substrate, where the interlayer dielectric includes a material that is substantially opaque to ultraviolet radiation.Type: GrantFiled: March 29, 2005Date of Patent: September 20, 2011Assignees: Spansion LLC, Advanced Micro Devices, Inc.Inventors: Minh Van Ngo, Wenmei Li, Jeffrey A. Shields, Ning Cheng, Angela Hui, Cinti Xiaohua Chen
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Patent number: 7977797Abstract: The present invention is a semiconductor contact formation system and method. Contact insulation regions are formed with multiple etch stop sublayers that facilitate formation of contacts. This contact formation process provides relatively small substrate connections while addressing critical lithographic printing limitation concerns in forming contact holes with small dimensions. In one embodiment, a multiple etch stop insulation layer comprising multiple etch stop layers is deposited. A contact region is formed in the multiple etch stop insulation layer by selectively removing (e.g., etching) some of the multiple etch stop insulation layer. In one embodiment, a larger portion of the multiple etch stop insulation layer is removed close to the metal layer and a smaller portion is removed closer to the substrate.Type: GrantFiled: August 11, 2009Date of Patent: July 12, 2011Assignee: Spansion LLCInventors: Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari
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Patent number: 7977218Abstract: Novel fabrication methods implement the use of dummy tiles to avoid the effects of in-line charging, ESD events, and such charge effects in the formation of a memory device region region. One method involves forming at least a portion of a memory core array upon a semiconductor substrate that involves forming STI structures in the substrate substantially surrounding a memory device region region within the array. An oxide layer is formed over the substrate in the memory device region region and over the STI's, wherein an inner section of the oxide layer formed over the memory device region region is thicker than an outer section of the oxide layer formed over the STI's. A first polysilicon layer is then formed over the inner and outer sections comprising one or more dummy tiles formed over one or more outer sections and electrically connected to at least one inner section.Type: GrantFiled: December 26, 2006Date of Patent: July 12, 2011Assignee: Spansion LLCInventors: Cinti Chen, Yi He, Wenmei Li, Zhizheng Liu, Ming-Sang Kwan, Yu Sun, Jean Yee-Mei Yang
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Patent number: 7951704Abstract: An integrated circuit memory device, in one embodiment, includes a substrate and first and second inter-level dielectric layers successively disposed on the substrate. One or more contacts in the peripheral extend through the first inter-level dielectric layer to respective components. One or more vias and a plurality of dummy vias extend through the second inter-level dielectric layer in the peripheral area. Each of the one or more peripheral vias extend to a respective peripheral contact. The peripheral dummy vias are located proximate the peripheral vias.Type: GrantFiled: July 30, 2009Date of Patent: May 31, 2011Assignee: Spansion LLCInventors: Shenqing Fang, Wenmei Li
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Patent number: 7927723Abstract: A film stack includes an interlayer dielectric formed over one or more devices. The film stack further includes a first layer having a high extinction coefficient formed on the interlayer dielectric and a second layer having a low extinction coefficient formed on the first layer. The first and second layers prevent ultraviolet induced damage to the one or more devices while minimizing reflectivity for lithographic processes.Type: GrantFiled: March 29, 2005Date of Patent: April 19, 2011Assignees: Spansion LLC, GlobalFoundries Inc.Inventors: Angela T. Hui, Ning Cheng, Minh Van Ngo, Hirokazu Tokuno, Wenmei Li
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Publication number: 20110057315Abstract: An integrated circuit memory device, in one embodiment, includes a substrate and first and second inter-level dielectric layers successively disposed on the substrate. One or more contacts in the peripheral extend through the first inter-level dielectric layer to respective components. One or more vias and a plurality of dummy vias extend through the second inter-level dielectric layer in the peripheral area. Each of the one or more peripheral vias extend to a respective peripheral contact. The peripheral dummy vias are located proximate the peripheral vias.Type: ApplicationFiled: November 10, 2010Publication date: March 10, 2011Inventors: Shenqing FANG, Wenmei LI
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Publication number: 20100276746Abstract: Methods for forming a memory cell are disclosed. A method includes forming a source-drain structure in a semiconductor substrate where the source-drain structure includes a rounded top surface and sidewall surfaces. An oxide layer is formed on the top and sidewall surfaces of the source-drain structure. The thickness of the portion of the oxide layer that is formed on the top surface of the source-drain structure is greater than the thickness of the portion of the oxide layer that is formed on the sidewall surfaces of the source-drain structure.Type: ApplicationFiled: April 29, 2009Publication date: November 4, 2010Inventors: Shenqing FANG, Gang XUE, Wenmei LI, Inkuk KANG
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Publication number: 20100207191Abstract: A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.Type: ApplicationFiled: February 13, 2009Publication date: August 19, 2010Applicant: Spansion LLCInventors: Shenqing FANG, Chun Chen, Wenmei Li, Inkuk Kang, Gang Xue, Hyesook Hong
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Patent number: 7704878Abstract: A contact structure in a semiconductor device includes a layer of dielectric material and a via formed through the dielectric material. The contact structure further includes a spacer formed on sidewalls of the via using atomic layer deposition (ALD) and a metal deposited in the via.Type: GrantFiled: October 3, 2005Date of Patent: April 27, 2010Assignees: Advanced Micro Devices, Inc,, Spansion LLCInventors: Minh Van Ngo, Angela T. Hui, Amol Ramesh Joshi, Wenmei Li, Ning Cheng, Ankur Bhushan Agarwal, Norimitsu Takagi
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Publication number: 20090294969Abstract: The present invention is a semiconductor contact formation system and method. Contact insulation regions are formed with multiple etch stop sublayers that facilitate formation of contacts. This contact formation process provides relatively small substrate connections while addressing critical lithographic printing limitation concerns in forming contact holes with small dimensions. In one embodiment, a multiple etch stop insulation layer comprising multiple etch stop layers is deposited. A contact region is formed in the multiple etch stop insulation layer by selectively removing (e.g., etching) some of the multiple etch stop insulation layer. In one embodiment, a larger portion of the multiple etch stop insulation layer is removed close to the metal layer and a smaller portion is removed closer to the substrate.Type: ApplicationFiled: August 11, 2009Publication date: December 3, 2009Inventors: Wenmei LI, Angela T. HUI, Dawn HOPPER, Kouros GHANDEHARI
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Publication number: 20090289369Abstract: An integrated circuit memory device, in one embodiment, includes a substrate and first and second inter-level dielectric layers successively disposed on the substrate. One or more contacts in the peripheral extend through the first inter-level dielectric layer to respective components. One or more vias and a plurality of dummy vias extend through the second inter-level dielectric layer in the peripheral area. Each of the one or more peripheral vias extend to a respective peripheral contact. The peripheral dummy vias are located proximate the peripheral vias.Type: ApplicationFiled: July 30, 2009Publication date: November 26, 2009Inventors: Shenqing FANG, Wenmei LI
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Patent number: 7572727Abstract: The present invention is a semiconductor contact formation system and method. Contact insulation regions are formed with multiple etch stop sublayers that facilitate formation of contacts. This contact formation process provides relatively small substrate connections while addressing critical lithographic printing limitation concerns in forming contact holes with small dimensions. In one embodiment, a multiple etch stop insulation layer comprising multiple etch stop layers is deposited. A contact region is formed in the multiple etch stop insulation layer by selectively removing (e.g., etching) some of the multiple etch stop insulation layer. In one embodiment, a larger portion of the multiple etch stop insulation layer is removed close to the metal layer and a smaller portion is removed closer to the substrate.Type: GrantFiled: September 2, 2004Date of Patent: August 11, 2009Assignee: Spansion LLCInventors: Wenmei Li, Angela T. Hui, Dawn Hopper, Kouros Ghandehari
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Publication number: 20080153269Abstract: The present invention pertains to a system and method for implementing dummy tiles in forming a memory device. The system and method involves forming at least a portion of a memory core array upon a semiconductor substrate comprising, forming STI structures in the substrate, depositing an oxide layer over the substrate, forming a first polysilicon layer over the oxide layer, doping the first polysilicon layer, forming a second polysilicon layer over the first polysilicon layer, patterning at least one memory core, patterning at least one dummy tile and performing back end processing.Type: ApplicationFiled: December 26, 2006Publication date: June 26, 2008Inventors: Cinti Chen, Yi He, Wenmei Li, Zhizheng Liu, Ming-Sang Kwan, Yu Sun, Jean Yee-Mei Yang
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Publication number: 20080096348Abstract: A memory device includes a number of memory cells and a dielectric layer formed over the memory cells. The memory device also includes contacts formed in the dielectric layer and spacers formed adjacent the side surfaces of the contacts. The spacers may inhibit leakage currents from the contacts.Type: ApplicationFiled: October 20, 2006Publication date: April 24, 2008Applicants: ADVANCED MICRO DEVICES, INC., SPANSION LLCInventors: Angela T. HUI, Wenmei LI, Minh Van NGO, Amol Ramesh JOSHI, Kuo-Tung CHANG