Patents by Inventor Wenning Wei

Wenning Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11508699
    Abstract: A display panel and a pixel structure are provided. The pixel structure includes a substrate, a micro light emitting diode (micro LED or ?LED), a sidewall structure, a filling layer, and a reflective layer. The substrate has a bearing surface, and the micro LED is disposed on the bearing surface directly or indirectly. The sidewall structure is disposed on the bearing surface and defines at least one accommodation cavity to accommodate the micro LED. The filling layer is filled in the accommodation cavity and surrounds the micro LED. The reflective layer covers a top surface of the filling layer and has a plurality of light-transmissible windows. The micro LED forms, in a vertical projection direction, a vertical projection region in an overlapping region on the reflective layer. Among the light-transmissible windows, those having longer distances to the vertical projection region have larger areas.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: November 22, 2022
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Pin-Miao Liu, Chen-Chang Chen, Wen-Wei Yang
  • Patent number: 11500648
    Abstract: A method for preparing fast boot of an information handling apparatus. The information handling apparatus contains a first CPU configured to connect to a storage device storing firmware and a second CPU connected to the first CPU. The method contains the steps of: allocating a firmware region in memories associated with each one of the first and second CPUs respectively; and copying a firmware from a storage device to the firmware region of each one of the memories. By utilizing a system memory such as NVDIMM which provides higher access speed than NAND flash and also persistent data storage, one or more CPUs can be booted from firmware images in the NVDIMM much faster, thus saving the total booting time.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: November 15, 2022
    Assignee: LENOVO ENTERPRISE SOLUTIONS (SINGAPORE) PTE. LTD.
    Inventors: Zhijun Liu, Chekim Chhuor, Wen Wei Tang
  • Patent number: 11502015
    Abstract: Semiconductor package includes interposer, dies, encapsulant. Each die includes active surface, backside surface, side surfaces. Backside surface is opposite to active surface. Side surfaces join active surface to backside surface. Encapsulant includes first material and laterally wraps dies. Dies are electrically connected to interposer and disposed side by side on interposer with respective backside surfaces facing away from interposer. At least one die includes an outer corner. A rounded corner structure is formed at the outer corner. The rounded corner structure includes second material different from first material. The outer corner is formed by backside surface and a pair of adjacent side surfaces of the at least one die. The side surfaces of the pair have a common first edge. Each side surface of the pair does not face other dies and has a second edge in common with backside surface of the at least one die.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: November 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Wei Shen, Sung-Hui Huang, Shang-Yun Hou, Kuan-Yu Huang
  • Publication number: 20220359335
    Abstract: Semiconductor package includes interposer, dies, encapsulant. Each die includes active surface, backside surface, side surfaces. Backside surface is opposite to active surface. Side surfaces join active surface to backside surface. Encapsulant includes first material and laterally wraps dies. Dies are electrically connected to interposer and disposed side by side on interposer with respective backside surfaces facing away from interposer. At least one die includes an outer corner. A rounded corner structure is formed at the outer corner. The rounded corner structure includes second material different from first material. The outer corner is formed by backside surface and a pair of adjacent side surfaces of the at least one die. The side surfaces of the pair have a common first edge. Each side surface of the pair does not face other dies and has a second edge in common with backside surface of the at least one die.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Wei Shen, Sung-Hui Huang, Shang-Yun Hou, Kuan-Yu Huang
  • Publication number: 20220336416
    Abstract: A package structure includes a circuit substrate and a semiconductor device. The semiconductor device is disposed on and electrically connected to the circuit substrate. The semiconductor device includes an interconnection structure, a semiconductor die, an insulating encapsulant, a protection layer and electrical connectors. The interconnection structure has a first surface and a second surface. The semiconductor die is disposed on the first surface and electrically connected to the interconnection structure. The insulating encapsulant is encapsulating the semiconductor die and partially covering sidewalls of the interconnection structure. The protection layer is disposed on the second surface of the interconnection structure and partially covering the sidewalls of the interconnection structure, wherein the protection layer is in contact with the insulating encapsulant.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Wei Shen, Sung-Hui Huang, Shang-Yun Hou
  • Patent number: 11469708
    Abstract: A ground-fault detecting device includes: a first detecting module, having a first input terminal, a second input terminal, and a third input terminal coupled to a first-phase electric power, a second-phase electric power, and a third-phase electric power on an AC side of a photovoltaic power generating system respectively, for sampling voltages of the first-phase electric power, the second-phase electric power, and the third-phase electric power to generate a first sampled voltage, a second sampled voltage, and a third sampled voltage respectively; and a controller, coupled to the first detecting module, for determining if a ground-fault occurs in the AC side before the photovoltaic power generating system is connected to a grid according to the first sampled voltage, the second sampled voltage, and the third sampled voltage; wherein the controller generates an alarm signal when the ground-fault occurs in the AC side.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: October 11, 2022
    Assignee: KEHUA HENGSHENG CO., LTD.
    Inventors: Chunbao Zeng, Peizai Hong, Wen Wei, Zhenhuang Lin, Kailong Chen
  • Publication number: 20220313138
    Abstract: A heart rhythm detection method and system by using radar sensor is capable of collecting an original signal using a radar sensor toward at least one subject, and converting the original signal to a two dimensional image information (i.e., spectrogram) using the concept of image vision. Then, the neural network automatically learns which heartbeat frequency should be focused on and which heartbeat frequency should be filtered out in the two dimensional image information through deep learning, so that the heartbeat frequencies can be extracted effectively.
    Type: Application
    Filed: March 30, 2021
    Publication date: October 6, 2022
    Inventors: Jing-Ming GUO, Ting LIN, Chia-Fen CHANG, Jeffry Susanto, Yi-Hsiang Lin, Po-Cheng Huang, Yu-Wen WEI
  • Publication number: 20220317280
    Abstract: A radar detection and identification device is disclosed, comprising at least one display host, at least one camera and at least one radar detector, wherein the camera and the radar detector, after photographing and detecting, are capable of performing masked face recognition and radar physiological detection recognition processes in order to identify the identity information and human physiological signals and display them on the display host.
    Type: Application
    Filed: March 30, 2021
    Publication date: October 6, 2022
    Inventors: Jing-Ming GUO, Ting LIN, Chia-Fen CHANG, Jeffry Susanto, Yi-Hsiang Lin, Po-Cheng Huang, Yu-Wen WEI
  • Publication number: 20220300231
    Abstract: A data transmitting method of a display device, which applies to a transmitting device and the display device. The transmitting device includes a first transmitting module. The display device includes a processing module, a second transmitting module, a storage module, and a display module. The data transmission method includes steps of: select a file on the transmitting device; compress the file to form a compressed file; send the compressed file to the display device via the first transmitting module; receive the compressed file by the second transmitting module of the display device; decompress the compressed file by the processing module to obtain the file; write the file into the storage module by the processing module and correspondingly displaying on the display module based on the file. In this way, a time for transmitting the file could be effectively reduced.
    Type: Application
    Filed: March 17, 2021
    Publication date: September 22, 2022
    Applicant: WINSTAR DISPLAY CO., LTD.
    Inventors: CHIA-HSIANG NI, WEN-WEI CHUNG, YU-CHANG SONG, CHIEN-CHOU HSU, WEN-HAO LIAO, YU-PIN LIAO
  • Publication number: 20220270242
    Abstract: Immune context scores are calculated for tumor tissue samples using continuous scoring functions. Feature metrics for at least one immune cell marker are calculated for a region or regions of interest, the feature metrics including at least a quantitative measure of human CD3 or total lymphocyte counts. A continuous scoring function is then applied to a feature vector including the feature metric and at least one additional metric related to an immunological biomarker, the output of which is an immune context score. The immune context score may then be plotted as a function of a diagnostic or treatment metric, such as a prognostic metric (e.g. overall survival, disease-specific survival, progression-free survival) or a predictive metric (e.g. likelihood of response to a particular treatment course). The immune context score may then be incorporated into diagnostic and/or treatment decisions.
    Type: Application
    Filed: January 5, 2022
    Publication date: August 25, 2022
    Inventors: Michael Barnes, Joerg Bredno, Rebecca C. Bowermaster, Srinivas Chukka, Wen-Wei Liu, Kandavel Shanmugam, Junming Zhu
  • Patent number: 11424219
    Abstract: A package structure includes a circuit substrate and a semiconductor device. The semiconductor device is disposed on and electrically connected to the circuit substrate. The semiconductor device includes an interconnection structure, a semiconductor die, an insulating encapsulant, a protection layer and electrical connectors. The interconnection structure has a first surface and a second surface. The semiconductor die is disposed on the first surface and electrically connected to the interconnection structure. The insulating encapsulant is encapsulating the semiconductor die and partially covering sidewalls of the interconnection structure. The protection layer is disposed on the second surface of the interconnection structure and partially covering the sidewalls of the interconnection structure, wherein the protection layer is in contact with the insulating encapsulant.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: August 23, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Wei Shen, Sung-Hui Huang, Shang-Yun Hou
  • Patent number: 11403242
    Abstract: The present invention provides a control method of multiple memory devices, wherein the multiple devices comprise a first memory device and a second memory device, and the control method includes the steps of: determining a first operation timing and a second operation timing according to at least a first command signal that a first memory controller needs to send to the first memory device; controlling the first memory controller to send the first command signal to the first memory device at the first operation timing; and controlling the second memory controller to send the second command signal to the second memory device at the second operation timing.
    Type: Grant
    Filed: February 7, 2021
    Date of Patent: August 2, 2022
    Assignee: Realtek Semiconductor Corp.
    Inventors: Ching-Sheng Cheng, Wen-Wei Lin, Kuan-Chia Huang
  • Patent number: 11396575
    Abstract: The present invention provides a thermoplastic polyurethane (TPU) having a glass transition temperature between an ambient temperature and normal body temperature, wherein the TPU contains dicarboxyphenyl polyester structure represented by Formula 1 or 10-(2,3-dicarboxypropyl)-9,10-dihydro-9-oxa-10-phosphaphenanthrene-10-oxide n(DOPO-ITA) polyester structure represented by Formula 2. The present invention also provides a polyester polyol containing DOPO-ITA polyester structure represented by Formula 2, a molar percentage of the 10-(2,3-dicarboxypropyl)-9,10-dihydro-9-oxa-10-oxide polyester structure in the whole polyester polyol ranges from 30% to 70%. The present invention further provides an article thereof. in Formula 1, R is C2 to C8 alkylene group or CH2CH2OCH2CH2; in Formula 2, R is C2 to C8 alkylene group or CH2CH2OCH2CH2.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: July 26, 2022
    Assignee: SUNKO INK CO., LTD.
    Inventors: Chiu-Peng Tsou, Zhen-Wei Chen, Wen-Wei Cheng, Ting-Ti Huang, Sheng-Mao Tseng
  • Patent number: 11376662
    Abstract: A method includes powder forging and machining a workpiece that is fractured to divide the workpiece into separate components. In a green form in which the workpiece is formed of compacted powdered metal and has a body that is generally shaped as a parallelepiped with a pair of end faces. The body defines a bore, a pair of V-notches and a pair of channels. The V-notches are formed into the bore parallel to the central axis of the bore and cooperate to define a separation plane. Each of the channels is formed in an associated one of the end faces at a location where the separation plane intersects the end face. During forging, the channels are closed but create a stress riser that aids in directing the fracture when the components are separated from one another.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: July 5, 2022
    Assignee: American Axle & Manufacturing, Inc.
    Inventors: Dejian Yan, Edwin Wen-Wei Zung
  • Publication number: 20220171961
    Abstract: The present invention provides an action recognition method and system thereof. The action recognition method comprises: capturing a 2D image and a depth image at the same time, extracting an 2D information of the human skeleton points from the 2D image and correcting it, mapping the 2D information of the human skeleton points to the depth image to obtain the corresponding depth information with respect to the 2D information of the human skeleton points and combining the corrected 2D information of the human skeleton points and the depth information to obtain the 3D information of the human skeleton points, and finally recognizing an action from a set of 3D information of the human skeleton points during a period of time by a matching model.
    Type: Application
    Filed: November 30, 2020
    Publication date: June 2, 2022
    Inventors: Jing-Ming GUO, Po-Cheng HUANG, Ting LIN, Chih-Hung WANG, Yu-Wen WEI, Yi-Hsiang LIN
  • Publication number: 20220147678
    Abstract: A method for capacitance extraction includes: performing a first capacitance extraction on one or more first regions of a semiconductor layout; performing a second capacitance extraction on one or more second regions of the semiconductor layout, a resolution of the second capacitance extraction being less than a resolution of the first capacitance extraction; constructing a netlist for the semiconductor layout based on results of the first capacitance extraction and of the second capacitance extraction; and modifying the semiconductor layout based on the netlist. The modified semiconductor layout is used to fabricate an integrated circuit.
    Type: Application
    Filed: June 30, 2021
    Publication date: May 12, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo Fu LEE, Ching Yang YEN, Ke-Ying SU, Chau-Wen WEI
  • Patent number: 11328535
    Abstract: The present invention provides an action recognition method and system thereof. The action recognition method comprises: capturing a 2D image and a depth image at the same time, extracting an 2D information of the human skeleton points from the 2D image and correcting it, mapping the 2D information of the human skeleton points to the depth image to obtain the corresponding depth information with respect to the 2D information of the human skeleton points and combining the corrected 2D information of the human skeleton points and the depth information to obtain the 3D information of the human skeleton points, and finally recognizing an action from a set of 3D information of the human skeleton points during a period of time by a matching model.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: May 10, 2022
    Assignee: IONETWORKS INC.
    Inventors: Jing-Ming Guo, Po-Cheng Huang, Ting Lin, Chih-Hung Wang, Yu-Wen Wei, Yi-Hsiang Lin
  • Patent number: 11318176
    Abstract: The present invention relates to a topical composition of facilitating wound healing and reducing scars, which includes an inactivated culture of Lactobacillus species as an effective ingredient and can significantly facilitate wound healing as well as reducing scars, thereby can be applied to a method of facilitating wound healing and reducing scars.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: May 3, 2022
    Assignee: GenMont Biotech Incorporation
    Inventors: Yi-Hsing Chen, Wan-Hua Tsai, Wen-Wei Chang, Chia-Hsuan Chou
  • Patent number: 11321232
    Abstract: A method for simultaneously accessing a first DRAM device and a second DRAM device includes the steps of: in an active phase, generating a first signal at a first pad, wherein the first signal is provided for the first DRAM device to select a first memory bank group, and the first signal is not for the second DRAM device to select any memory bank group; and generating a second signal at the first pad, wherein the second signal is provided for the first DRAM device to select the first bank group, and the second signal and the first signal correspond to a same digital value.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: May 3, 2022
    Assignee: Realtek Semiconductor Corp.
    Inventors: Wen-Wei Lin, Kuan-Chia Huang, Ching-Sheng Cheng
  • Publication number: 20220091112
    Abstract: A microbead with a code engraved on an outside of the microbead. The microbead includes a central region and an edge region surrounding the central region. An outer contour of the edge region before and after engraving the code is non-circular. The edge region includes a plurality of coding positions. The code of the microbead is engraved on the plurality of coding positions. Each bit of the code corresponds to each of the plurality of coding positions. The present disclosure increases the utilization rate of the microbead.
    Type: Application
    Filed: January 23, 2019
    Publication date: March 24, 2022
    Inventors: WEN-WEI ZHANG, WEI CHEN, WEI-MAO WANG, MEI LI, YU-XIANG LI, JIAN WANG