Patents by Inventor Wen-Pin Lu
Wen-Pin Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11967546Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.Type: GrantFiled: July 21, 2022Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shang-Yun Hou, Hsien-Pin Hu, Sao-Ling Chiu, Wen-Hsin Wei, Ping-Kang Huang, Chih-Ta Shen, Szu-Wei Lu, Ying-Ching Shih, Wen-Chih Chiou, Chi-Hsi Wu, Chen-Hua Yu
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Publication number: 20210272877Abstract: A semiconductor device includes a substrate, at least one heterojunction bipolar transistor including a semiconductor unit and an electrode unit, an insulation unit, and a heat dissipation unit. The insulation unit covers the substrate and the heterojunction bipolar transistor such that a collector electrode, a base electrode and an emitter electrode of the electrode unit are electrically isolated from one another. The insulation unit is formed with an opening to expose an electrode wire of the emitter electrode. The heat dissipation unit covers the electrode wire and is made of an electrically conductive and heat dissipating material, and has a thickness that is not less than 3 ?m.Type: ApplicationFiled: September 18, 2020Publication date: September 2, 2021Inventors: You-Min CHI, Kuo-Chun HUANG, Kun-Mu HSIEH, Yu-Chen CHIU, Chi-Chun LIN, Wen-Pin LU, Chao-Hung CHEN
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Publication number: 20210104477Abstract: A pad structure includes a conductive layer, a pad layer, a protective layer and a dielectric layer. The conductive layer is located above the substrate. The protective layer covers the pad layer and has an opening to expose a portion of the pad layer. The dielectric layer is formed between the conductive layer and the pad layer and between the conductive layer and the pad layer. The conductive layer includes a number of effective blocks, and a proportion of a block area of a block of the effective blocks to a total block area of the effective blocks ranges between 40%-50%. The block has at least one hollow portion, wherein the hollow portion has a total hollow area, and a ratio of the total hollow area to the block area ranged between 0.1 and 0.5.Type: ApplicationFiled: October 4, 2019Publication date: April 8, 2021Inventors: Chih-Ching Eric SHIH, Hung-Chi CHEN, Li-Kuang KUO, Wen-Pin LU
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Publication number: 20170098478Abstract: A method, apparatus and computer program product are provided in order to test word line failure of a non-volatile memory device. An example of the method includes performing a failure screening of the non-volatile memory device, wherein the non-volatile memory device comprises one or more word lines; identifying a point of failure located between a first word line and a second word line; and marking the first word line and the second word line as a single word line in response to identifying the point of failure between the first word line and the second word line.Type: ApplicationFiled: October 2, 2015Publication date: April 6, 2017Inventors: Chih-Wei Lee, Cheng-Hsien Cheng, Shaw-Hung Ku, Wen-Pin Lu
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Publication number: 20170077118Abstract: Embodiments of the present invention provide improved three-dimensional memory cells, arrays, devices, and/or the like and associated methods. In one embodiment, a three-dimensional memory cell is provided. The three-dimensional memory cell comprises a first conductive layer; a third conductive layer spaced apart from the first conductive layer; a channel conductive layer connecting the first conductive layer and the third conductive layer to form an opening having internal surfaces; a dielectric layer disposed along the internal surfaces of the opening surrounded by the first conductive layer, the channel conductive layer and the third conductive layer; and a second conductive layer interposed and substantially filling a remaining open portion formed by the dielectric layer. The first conductive layer, the dielectric layer, and the second conductive layer are configured to form a staircase structure.Type: ApplicationFiled: September 15, 2015Publication date: March 16, 2017Inventors: CHENG-HSIEN CHENG, CHIH-WEI LEE, SHAW-HUNG KU, WEN-PIN LU
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Patent number: 9589982Abstract: Embodiments of the present invention provide improved three-dimensional memory cells, arrays, devices, and/or the like and associated methods. In one embodiment, a three-dimensional memory cell is provided. The three-dimensional memory cell comprises a first conductive layer; a third conductive layer spaced apart from the first conductive layer; a channel conductive layer connecting the first conductive layer and the third conductive layer to form an opening having internal surfaces; a dielectric layer disposed along the internal surfaces of the opening surrounded by the first conductive layer, the channel conductive layer and the third conductive layer; and a second conductive layer interposed and substantially filling a remaining open portion formed by the dielectric layer. The first conductive layer, the dielectric layer, and the second conductive layer are configured to form a staircase structure.Type: GrantFiled: September 15, 2015Date of Patent: March 7, 2017Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Cheng-Hsien Cheng, Chih-Wei Lee, Shaw-Hung Ku, Wen-Pin Lu
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Patent number: 9524784Abstract: The present invention provides methods and associated devices for controlling the voltage threshold distribution corresponding to performing a function on cells of non-volatile memory device. In one embodiment, a method is provided. The method may comprise providing the non-volatile memory device. The device comprises one or more strings, each string comprising a plurality of cells, the plurality of cells comprising a first cell and a second cell. The method further comprises performing a function of the non-volatile memory device by applying a first function voltage to the first cell and a second function voltage to the second cell. The first function voltage and the second function voltage are different.Type: GrantFiled: September 9, 2015Date of Patent: December 20, 2016Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Cheng-Hsien Cheng, Chih-Wei Lee, Shaw-Hung Ku, Wen-Pin Lu
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Publication number: 20160336339Abstract: Embodiments of the present invention provide improved 3D non-volatile memory devices and associated methods. In one embodiment, a string of 3D non-volatile memory cells is provided. The string comprises a core extending along an axis of the string, the core having an elliptical cross section in a plane perpendicular to the axis; and a plurality of word lines, each word line disposed around a part of the core, the plurality of word lines spaced along the axis, and each word line corresponding to one of the memory cells. In various embodiments, at least one operating parameter is defined in order to improve the operation of the 3D non-volatile memory device.Type: ApplicationFiled: October 13, 2015Publication date: November 17, 2016Inventors: Cheng-Hsien Cheng, Chih-Wei Lee, Shaw-Hung Ku, Wen-Pin Lu
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Patent number: 9437612Abstract: A three-dimensional memory, which includes memory cell stacked structures. The memory cell stacked structures are stacked by a plurality of memory cell array structures and insulation layers alternatively, and each memory cell array structure includes word lines, active layers, composite layers and sources/drains. The word lines, the active layers and the composite layers extend along a Y direction. The active layers are disposed between the adjacent word lines. The composite layers are disposed between the adjacent word lines and the adjacent active layers, and each composite layer includes a first dielectric layer, a charge storage layer and a second dielectric layer in sequence from the active layers. The sources/drains are disposed in the active layers at equal intervals. A memory cell includes two adjacent sources/drains, the active layer between the two adjacent sources/drains, the first dielectric layer, the charge storage layer and the second dielectric layer on the active layer, and the word lines.Type: GrantFiled: August 21, 2015Date of Patent: September 6, 2016Assignee: MACRONIX International Co., Ltd.Inventors: Chih-Wei Lee, Cheng-Hsien Cheng, Shaw-Hung Ku, Wen-Pin Lu
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Patent number: 9383990Abstract: A server includes a detecting module, a calculating module, a comparing module, an allocating module and a sorting module. The detecting module is used for receiving firmware version query information from a plurality of client devices. The calculating module is used for calculating bandwidth sum of the CPEs. The comparing module is used for determining whether the calculated total bandwidth is larger than a total downloading bandwidth of the server. The allocating module is used for sequencing the client devices which transmit the firmware download requests to wait for the download. The sorting module is used for scoring each of the client devices which transmit the firmware download requests according to attributes of the client devices which transmit the firmware download requests and sequencing the client devices which transmit the firmware download requests to wait for downloading according to the scores.Type: GrantFiled: September 16, 2014Date of Patent: July 5, 2016Assignee: HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Wen-Pin Lu, Ming-Chen Tsai
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Publication number: 20160062759Abstract: A server includes a detecting module, a calculating module, a comparing module, an allocating module and a sorting module. The detecting module is used for receiving firmware version query information from a plurality of client devices. The calculating module is used for calculating bandwidth sum of the CPEs. The comparing module is used for determining whether the calculated total bandwidth is larger than a total downloading bandwidth of the server. The allocating module is used for sequencing the client devices which transmit the firmware download requests to wait for the download. The sorting module is used for scoring each of the client devices which transmit the firmware download requests according to attributes of the client devices which transmit the firmware download requests and sequencing the client devices which transmit the firmware download requests to wait for downloading according to the scores.Type: ApplicationFiled: September 16, 2014Publication date: March 3, 2016Inventors: WEN-PIN LU, MING-CHEN TSAI
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Patent number: 8466064Abstract: A system, method, and layout for a semiconductor integrated circuit device allows for improved scaling down of various back-end structures, which can include contacts and other metal interconnection structures. The resulting structures can include a semiconductor substrate, a buried diffusion region formed on the semiconductor substrate, and at least one of a silicide film, for example tungsten silicide (WSix), and a self-aligned silicide (salicide) film, for example cobalt silicide (CoSi) and/or nickel silicide (NiSi), above the buried diffusion (BD) layer. The semiconductor integrated circuit can also include a memory gate structure formed over at least a portion of the contact layer.Type: GrantFiled: November 12, 2010Date of Patent: June 18, 2013Assignee: Macronix International Co., Ltd.Inventors: Yu-Fong Huang, Tzung-Ting Han, Wen-Pin Lu
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Patent number: 8466508Abstract: A non-volatile memory structure including a substrate, stacked patterns and stress patterns is provided. The stacked patterns are disposed on the substrate. Each of the stacked patterns includes a charge storage structure and a gate from bottom to top. Here, the charge storage structure at least includes a charge storage layer. The stress patterns are disposed on the substrate between the two adjacent stacked patterns, respectively.Type: GrantFiled: October 3, 2007Date of Patent: June 18, 2013Assignee: MACRONIX International Co., Ltd.Inventors: Shaw-Hung Ku, Shih-Chin Lee, Chia-Wei Wu, Shang-Wei Lin, Tzung-Ting Han, Ming-Shang Chen, Wen-Pin Lu
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Patent number: 8451641Abstract: A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, and a plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The plug is located between the dummy word line and the outmost word line.Type: GrantFiled: July 13, 2012Date of Patent: May 28, 2013Assignee: MACRONIX International Co., Ltd.Inventors: Chun-Yuan Lo, Cheng-Ming Yih, Wen-Pin Lu
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Publication number: 20120273842Abstract: A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, and a plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The plug is located between the dummy word line and the outmost word line.Type: ApplicationFiled: July 13, 2012Publication date: November 1, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chun-Yuan Lo, Cheng-Ming Yih, Wen-Pin Lu
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Patent number: 8243489Abstract: A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, at least a first conductive region and at least a first plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The first conductive region is disposed only between the dummy word line and the outmost word line. The first plug is located between the dummy word line and the outmost word line.Type: GrantFiled: March 10, 2011Date of Patent: August 14, 2012Assignee: MACRONIX International Co., Ltd.Inventors: Chun-Yuan Lo, Cheng-Ming Yih, Wen-Pin Lu
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Publication number: 20120119282Abstract: A system, method, and layout for a semiconductor integrated circuit device allows for improved scaling down of various back-end structures, which can include contacts and other metal interconnection structures. The resulting structures can include a semiconductor substrate, a buried diffusion region formed on the semiconductor substrate, and at least one of a silicide film, for example tungsten silicide (WSix), and a self-aligned silicide (salicide) film, for example cobalt silicide (CoSi) and/or nickel silicide (NiSi), above the buried diffusion (BD) layer. The semiconductor integrated circuit can also include a memory gate structure formed over at least a portion of the contact layer.Type: ApplicationFiled: November 12, 2010Publication date: May 17, 2012Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Yu-Fong Huang, Tzung-Ting Han, Wen-Pin Lu
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Publication number: 20110156102Abstract: A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, at least a first conductive region and at least a first plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The first conductive region is disposed only between the dummy word line and the outmost word line. The first plug is located between the dummy word line and the outmost word line.Type: ApplicationFiled: March 10, 2011Publication date: June 30, 2011Applicant: MACRONIX International Co., Ltd.Inventors: CHUN-YUAN LO, Cheng-Ming Yih, Wen-Pin Lu
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Patent number: 7924591Abstract: A memory device is provided. The memory device comprises a substrate, a plurality of word lines, a plurality of conductive regions and at least a shielding plug. The substrate has a memory region and a peripheral region. The word lines are disposed on the substrate and at least a dummy word line disposed in the peripheral region and adjacent to the word lines. The conductive regions are disposed in the substrate and between the word lines respectively. The shielding plug is located on the substrate and adjacent to the dummy word line and between the dummy word line and the word lines and there is no self-aligned source region around the dummy word line.Type: GrantFiled: February 6, 2009Date of Patent: April 12, 2011Assignee: MACRONIX International Co., Ltd.Inventors: Chun-Yuan Lo, Cheng-Ming Yih, Wen-Pin Lu
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Patent number: 7847336Abstract: Methods are described for fabricating NAND-type EEPROMs without field oxide isolation. P+ implantations are employed to isolate adjacent memory cells.Type: GrantFiled: May 30, 2008Date of Patent: December 7, 2010Assignee: Macronix International Co., Ltd.Inventors: Ming-Shang Chen, Wen-Pin Lu