Abstract: A biomedical implant is provided for simultaneously generating multiple voltages for digital and analog circuits. Two AC voltages induced from an external single AC source located externally to the biomedical implant are used as input to a multi-voltage rectifier. The multi-voltage rectifier has a rectifier circuitry for simultaneously generating: (i) both low positive and negative voltages and (ii) both high positive and negative voltages. A startup circuitry is designed to stabilize both low positive and negative voltages prior to stabilizing both high positive and negative voltages. A timing control circuitry is used to prevent reverse leakage currents from loading capacitors to input for efficiency enhancement. The biomedical implant, by virtue of the multi-voltage timing control rectifier, achieves high power transfer efficiency greater than 85%.

Abstract: A high channel count high-voltage neural stimulator provides an external circuit which communicates power and data to a neural stimulator implant circuit. Data from the external device, such as image data from a camera in an epiretinal application, are communicated to the implant. Multiple pixels circuits, within each implant demultiplex the digital signals, then output separate nerve stimulator outputs from multiple outputs, each configured for connection to a nerve, by sharing a single level conversion driver circuit. In at least one example, the implant circuits can be clustered in a master-slave configuration to increase the number of available neural stimulation outputs.

Abstract: Neural signal recording apparatus and method is described, in which a micro electrode array is utilized for performing a weighted matrix as a moving window providing superpositioning of electrode signals. A voltage distribution across the electrode array is determined as a Laplacian. The apparatus and method can be utilized in a variety of electrode sensing applications involving registering neural activity, and for electrode stimulation applications, or combinations thereof.

Abstract: An apparatus and method for electrical charge balancing when generating a stimulus during functional neural stimulation is presented. A stimulus pulse is generated (cathodic or anodic), and after a selected delay a charge compensating pulse is generated of an opposite polarity. The electrode circuit discontinuously examines electrode voltage after termination of the stimulus pulse, and utilizes this voltage to determine how long to extend the width of the charge compensating pulse. The electrode circuit thus performs accurate electrical charge cancellation to remove residual charges from the electrode by precisely controlling pulse width for an opposing polarity compensating pulse that need not have the same current level as the stimulus pulse.

Abstract: A high channel count high-voltage neural stimulator provides an external circuit which communicates power and data to a neural stimulator implant circuit. Data from the external device, such as image data from a camera in an epiretinal application, are communicated to the implant. Multiple pixels circuits, within each implant demultiplex the digital signals, then output separate nerve stimulator outputs from multiple outputs, each configured for connection to a nerve, by sharing a single level conversion driver circuit. In at least one example, the implant circuits can be clustered in a master-slave configuration to increase the number of available neural stimulation outputs.

Abstract: A neuron recording system was provided. By using the gain-boosted topology, the amplifier input impedance can be increased while simultaneously reducing the noise. The system can be configured to record local field potentials (LFPs) and neuron spikes, respectively, with low-power consumption. With the flexible digital controller module (DCM), any subset of the recording channels can be activated for recording with independent sampling rate at each channel. A wireless interface to transmit recorded neuron data and an on-chip neuron processor to perform real-time signal processing can be incorporated in the system.

Abstract: Epileptogenic source localization methods and systems based on ECoG signals are provided for obtaining spatial and temporal relationships among epileptogenic zones. Seizure detection is based on an Independent Component Analysis (ICA) and temporal and spatial relationships among the detected epileptogenic zones are based on a steepest descent-based source localization method. Embodiments of the invention facilitate the epileptiform activity investigation and seizure dynamics study and further benefit the neurophysiology community in the surgical decision making of neurosurgeons.

Abstract: A biomedical implant is provided for simultaneously generating multiple voltages for digital and analog circuits. Two AC voltages induced from an external single AC source located externally to the biomedical implant are used as input to a multi-voltage rectifier. The multi-voltage rectifier has a rectifier circuitry for simultaneously generating: (i) both low positive and negative voltages and (ii) both high positive and negative voltages. A startup circuitry is designed to stabilize both low positive and negative voltages prior to stabilizing both high positive and negative voltages. A timing control circuitry is used to prevent reverse leakage currents from loading capacitors to input for efficiency enhancement. The biomedical implant, by virtue of the multi-voltage timing control rectifier, achieves high power transfer efficiency greater than 85%.

Abstract: Devices, systems and methods are provided for directly stimulating tissues, particularly muscle tissues, to modulate muscle contractions (i.e. provide reanimation of the muscle or to suppress undesired muscle contractions). Reanimation of muscles may be desired when damage to the brain, nervous system or neuromuscular junctions have occurred, causing a muscle tissue to lack sufficient motor control. Suppression of muscle contractions may be desired in situations of pathologically hyperactive muscles, such as in conditions of muscle spasm (e.g. blepharospasm and hemifacial spasm) or muscle dystonia. Direct stimulation is achieved by delivering a chemical agent directly to the muscle tissue, particularly the motor end plate, bypassing the nerves and neuromuscular junctions which may be damaged or diseased. Implanted hybrid chemical and electromagnetic stimulation devices can modulate muscle contraction in response to signals from a controller.

Abstract: A method and system for is disclosed for reducing intersymbol interference in a stream of data bits to be transmitted over a transmission medium. Aspects of the present invention include a phase delayed clock generated from a reference clock that produces an edge on sub-bit boundaries; and a digital filter coupled to the phase delayed clock for performing equalization on the data bits, wherein the phase delayed clock causes the digital filter to perform partial clock switching, such that equalization is performed on the data bits on-sub-bit boundaries.

Abstract: An adaptive bandwidth bus is provided that switches between a current mode of operation and a voltage mode of operation. Furthermore, related methods include transmitting a data signal in a current mode or a voltage mode and transmitting a control signal to indicate whether the signal should be transmitted in the current mode or the voltage mode.

Abstract: A method and system for is disclosed for reducing intersymbol interference in a stream of data bits to be transmitted over a transmission medium. Aspects of the present invention include a phase delayed clock generated from a reference clock that produces an edge on sub-bit boundaries; and a digital filter coupled to the phase delayed clock for performing equalization on the data bits, wherein the phase delayed clock causes the digital filter to perform partial clock switching, such that equalization is performed on the data bits on-sub-bit boundaries.

Abstract: A circuit includes a first pre-amp circuit that provides a first pre-amp current and a second pre-amp circuit that provides a second pre-amp current. A first threshold circuit is configured to generate a first output signal responsive to a difference between a variable current and the first pre-amp current. A second threshold circuit is configured to generate a second output signal responsive to a difference between the variable current and the second pre-amp current. One of the branches of a differential interpolation circuit includes a first transistor that is connected in a current mirror configuration with the first pre-amp circuit. The first transistor has a width/length ratio equal to the product nk, where n<1. A second transistor is connected in a current mirror configuration with the second pre-amp circuit. The second transistor has a width/length ratio equal to the product mk, where m<1 and n+m is about 1.

Abstract: An adaptive bandwidth bus is provided that switches between a current mode of operation and a voltage mode of operation. Furthermore, related methods include transmitting a data signal in a current mode or a voltage mode and transmitting a control signal to indicate whether the signal should be transmitted in the current mode or the voltage mode.

Abstract: A circuit includes a first pre-amp circuit that provides a first pre-amp current and a second pre-amp circuit that provides a second pre-amp current. A first threshold circuit is configured to generate a first output signal responsive to a difference between a variable current and the first pre-amp current. A second threshold circuit is configured to generate a second output signal responsive to a difference between the variable current and the second pre-amp current. One of the branches of a differential interpolation circuit includes a first transistor that is connected in a current mirror configuration with the first pre-amp circuit. The first transistor has a width/length ratio equal to the product nk, where n<1. A second transistor is connected in a current mirror configuration with the second pre-amp circuit. The second transistor has a width/length ratio equal to the product mk, where m<1 and n+m is about 1.

Abstract: Integrated circuits having cooperative ring oscillator clock circuits therein include a plurality of synchronous and asynchronous active devices on the substrate and a plurality of "cooperative" ring oscillators (CRO) electrically coupled in parallel at respective clock nodes, interspersed on the substrate as a mesh, for example. The ring oscillators, which may have a predetermined number of stages but possibly different size in terms of clock driving capability, are preferably interspersed among the synchronous active devices on the surface of the substrate to provide a "local" clock signal which is constrained in terms of skew and jitter by the presence of the other parallel-connected ring oscillators at other locations on the substrate. Multiple replications of a ring-oscillator containing three serially connected inverters may result in the formation of a two-dimensional hexagonal network of clock nodes of different phases (e.g., .phi..sub.1, .phi..sub.2 and .phi..sub.3).

Abstract: A data signal may be sampled at high speed using a clock signal by propagating the data signal and the clock signal through a series of data and clock delay elements, respectively, and latching the corresponding delayed data and clock signals. The sampling speed is thereby controlled by the relative skew between the clock and data signals, which can be made relatively small and may be limited only by noise and random variations in fabrication. Accordingly, high speed sampling may be obtained.

Abstract: A method and apparatus for rasterizing a two-dimensional fast Fourier transform of a size N.times.N using a pipelined butterfly computational unit with 2logN processors. The invention avoids the problems associated with transposing the matrix so that the data can be continuously driven into the arithmetic processors in a pipelined fashion. It is devised for realtime applications using raster scan or serial input and output devices.

Abstract: A novel architecture and circuitry for implementing a new fast fourier transform algorithm which does not require a very large core memory and also does not require a transpose of a matrix. A pipelined and parallel architecture implements the two dimensional fast fourier transform on an array of input data values, with the transformation being performed by a plurality of serially arranged pass stages. Each pass stage includes an input shuffle arrangement for receiving an ordered set of input data from a row or column of a two dimensional matrix of such input data values, and for performing a shuffle operation thereon to produce a shuffled order of the input data. Each pass stage further includes a plurality of identical switching circuits coupled in parallel to receive the shuffled order of input data.