Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A sacrificial layer on a substrate, a first stop layer on the sacrificial layer, an N-type doped semiconductor layer on the first stop layer, and a dielectric stack on the N-type doped semiconductor layer are sequentially formed. A plurality of channel structures each extending vertically through the dielectric stack and the N-type doped semiconductor layer are formed, stopping at the first stop layer. The dielectric stack is replaced with a memory stack, such that each of the plurality of channel structures extends vertically through the memory stack and the N-type doped semiconductor layer. The substrate, the sacrificial layer, and the first stop layer are sequentially removed to expose an end of each of the plurality of channel structures. A conductive layer is formed in contact with the ends of the plurality of channel structures.

Abstract: A semiconductor device includes a first stack of layers stacked on a substrate. The first stack of layers includes a source connection layer that is formed by replacing source sacrificial layers. The semiconductor device includes a channel structure that extends in the first stack of layers. The channel structure includes a channel layer that is in contact with the source connection layer in the first stack of layers. Further, the semiconductor device includes a shield structure formed in the first stack of layers. The shied structure encloses a stack of layers without the source connection layer.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes channel structures in a first region and word line pick-up structures in a first portion of a second region. The first region and the second region are arranged in a first direction. The 3D memory device also includes word lines each extending in the first region and a second portion of the second region. The first portion and the second portion of the second region are arranged in a second direction perpendicular to the first direction. The 3D memory device also includes dummy channel structures in the second portion of the second region. Adjacent channel structures are spaced apart from each other by a first distance. Adjacent dummy channel structures are spaced apart from each other by a second distance that is smaller than the first distance.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes channel structures in a first region, word line pick-up structures in a dielectric portion of a second region, and word lines each extending in the first region and a conductive portion of the second region. The first region and the second region are arranged in a first direction. The dielectric portion and the conductive portion of the second region are arranged in a second direction perpendicular to the first direction. The word lines are discontinuous in the dielectric portion of the second region and are electrically connected to the word line pick-up structures, respectively.

Abstract: In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A stack structure including interleaved first dielectric layers and second dielectric layers is formed. Channel structures extending through the first dielectric layers and the second dielectric layers in a first region of the stack structure are formed. All the second dielectric layers in the first region and parts of the second dielectric layers in a second region of the stack structure are replaced with conductive layers. Word line pick-up structures extending through the first dielectric layers and remainders of the second dielectric layers in the second region of the stack structure are formed at different depths, such that the word line pick-up structures are electrically connected to the conductive layers, respectively, in the second region of the stack structure.

Abstract: A method for data erasing of a non-volatile memory device is disclosed. The memory includes multiple memory cell strings each including a select gate transistor and multiple memory cells that are connected in series. The method comprises applying a step erase voltage to one memory cell string for an erase operation, the step erase voltage having a step-rising shaped voltage waveform. The method further comprises, during a period when the step erase voltage rises from an intermediate level to a peak level, raising a voltage of the select gate transistor from a starting level to a peak level, and raising a voltage of a predetermined region from a starting level to a peak level, such that a gate-induced drain leakage current is generated in the one memory cell string. The predetermined region is adjacent to the at least one select gate transistor and includes at least one memory cell.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells, a first peripheral circuit of the array of memory cells, and a polysilicon layer between the array of memory cells and the first peripheral circuit. The first peripheral circuit includes a first transistor. The second semiconductor structure includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, and a first bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells. The second semiconductor structure includes a first peripheral circuit of the array of memory cells. The first peripheral circuit includes a first transistor. A third semiconductor structure includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor. The first semiconductor structure, the second semiconductor structure, and the third semiconductor structure are stacked over one another.

Abstract: A memory device includes a stack structure, channel structures, and a slit structure. The stack structure includes interleaved conductive layers and dielectric layers, and the conductive layers include a plurality of word lines. Each of the channel structures extends vertically through the stack structure. The slit structure extends vertically through the stack structure. An outer region of the stack structure includes a staircase structure, and the interleaved conductive layers and dielectric layers in a bottom portion of the stack structure are wider than the interleaved conductive layers and dielectric layers in a top portion of the stack structure. A first outer width of the slit structure in the bottom portion of the stack structure is greater than a second outer width of the slit structure in the top portion of the stack structure.

Abstract: In a semiconductor device, a stack of alternating gate layers and insulating layers is formed. Channel structures are formed in an array region of the stack. A first staircase is formed at a first section of the stack. A second staircase is formed at a second section of the stack. A dummy staircase is formed at the first section and disposed between the first staircase and the second staircase. The dummy staircase includes dummy group stair steps descending in a second direction parallel to a plane defined by any one of the gate layers and the insulating layers, and dummy division stair steps descending in a third direction and a fourth direction parallel to the plane and perpendicular to the second direction. The third direction and the fourth direction are opposite to each other.

Abstract: A three-dimensional (3D) memory device includes a stack, a plurality of contact structures, and a plurality of support structures. The stack in an insulating structure includes a plurality of conductive layers and a plurality of dielectric layers stacked alternatingly, and the stack includes a staircase structure. The plurality of contact structures each extends through the insulating structure and in contact with a respective conductive layer of the plurality of conductive layers in the staircase structure. The plurality of support structures extends through the stack in the staircase structure. Each support structure is in contact with one of the plurality of contact structures.

Abstract: A three-dimensional (3D) memory device includes a stack, a plurality of contact structures, and a plurality of support structures. The stack in an insulating structure includes conductive layers and dielectric layers stacked alternatingly, and the stack includes a staircase structure. Each contact structure extends through the insulating structure and is in contact with a respective conductive layer in the staircase structure. The support structures extend through the stack in the staircase structure. The contact structures are arranged in a first row and a second row, the first row of contact structures is in electrical contact with the peripheral device, and the second row of contact structures is in electrical insulation with the peripheral device.

Abstract: A three-dimensional (3D) memory device includes a core array region and a staircase region adjacent to the core array region. The core array region includes a memory stack having a plurality of conductor layers and a plurality of dielectric layers stacked alternatingly, a first semiconductor layer disposed over the memory stack, and a channel structure extending through the memory stack and the first semiconductor layer. The staircase region includes a staircase structure, a supporting structure disposed over the staircase structure, and a plurality of contacts contacting the plurality of conductor layers in the staircase structure. The first semiconductor layer overlaps the core array region in a plan view of the 3D memory device and the supporting structure overlaps the staircase region in the plan view of the 3D memory device.

Abstract: In a method for fabricating a semiconductor device, an initial stack of sacrificial word line layers and insulating layers is formed over a substrate of the semiconductor device. The sacrificial word line layers and the insulating layers are disposed over the substrate alternately. A first staircase is formed in a first staircase region of a connection region of the initial stack. A second staircase is formed in a second staircase region of the connection region of the initial stack. The connection region of the initial stack includes a separation region between the first and second staircases, and the connection region is positioned between array regions of the initial stack at opposing sides of the initial stack.

Abstract: A 3D includes a memory array structure. The memory array structure includes a first memory array structure and a second memory array structure each having a plurality of conductive/dielectric layer pairs. The memory array structure also includes a staircase structure between the first memory array structure and the second memory array structure. The staircase structure includes a first staircase zone and a second staircase zone. The first staircase zone includes at least one staircase, each including a plurality of stairs. The second staircase zone includes a bridge structure, and at least one other staircase over the bridge structure. The bridge structure connects the first memory array structure and the second memory array structure, the at least one other staircase each including a plurality of stairs. At least one stair in one or more of the at least one staircase is electrically connected to the bridge structure.

Abstract: A method for forming a three-dimensional memory device can include forming a staircase structure. An alternating layer stack is disposed and etched to form steps. A continuous layer disposed on the staircase structure continuously extends over the steps. An insulating layer is disposed on the continuous layer and a slit is formed extending through the staircase structure. The slit exposes sidewalls of the continuous layer and the steps. The sacrificial layer is removed and a cavity is formed in place of the continuous layer. An etch stop layer is disposed in the cavity and continuously extends over the steps. Openings are formed through the insulating layer and expose a portion of a lateral surface of the etch stop layer. The openings are extended through the etch stop layer to expose a lateral surface of each step of the steps. Contacts are formed in the openings.

Abstract: A semiconductor device semiconductor device includes a stack having a first surface and a second surface opposing the first surface. The stack can include word line layers and insulating layers alternating with the word line layers between the first surface and the second surface. The stack can further include a process stop layer between the lower most insulating layer and the second surface. The stack can extend along an X-Y plane having an X direction and a Y direction perpendicular. The semiconductor device can further include a slit structure crossing the stack between the first surface and the second surface in Z direction. In a cross-section perpendicular to the Y direction, distances between the slit structure and the process stop layer at two sides of the slit structure are each larger than distances at either side of the slit structure between the word line layers and the slit structure.

Abstract: The disclosure provides an erase method for a memory device. In the method, during a time period, a first positive voltage is applied to a body portion of a memory cell string of the memory device. The memory cell string includes memory cell transistors and select transistors connected in series. A second positive voltage is applied to a bit line signal of the memory cell string. A third positive voltage is applied to a first top select gate signal to turn on a first top select transistor of the select transistors so that the memory cell transistors are coupled to the bit line signal through the first top select transistor. A ground level voltage or a fourth positive voltage is applied to a word line signal of the memory cell transistors. Both the third and fourth positive voltages are less than the second positive voltage.

Abstract: In a semiconductor device, a stack of alternating gate layers and insulating layers is formed. Channel structures are formed in an array region of the stack. A first staircase is formed at a first section of the stack. A second staircase is formed at a second section of the stack. A dummy staircase is formed at the first section and disposed between the first staircase and the second staircase. The dummy staircase includes dummy group stair steps descending in a second direction parallel to a plane defined by any one of the gate layers and the insulating layers, and dummy division stair steps descending in a third direction and a fourth direction parallel to the plane and perpendicular to the second direction. The third direction and the fourth direction are opposite to each other.

Abstract: Embodiments of 3D memory structures and methods for forming the same are disclosed. The fabrication method includes disposing an alternating dielectric stack on a substrate, wherein the alternating dielectric stack having first and second dielectric layers alternatingly stacked on top of each other. Next, a plurality of contact openings can be formed in the alternating dielectric stack such that a dielectric layer pair can be exposed inside at least one of the plurality of contact openings. The method further includes forming a film stack of alternating conductive and dielectric layers by replacing the second dielectric layer with a conductive layer, and forming a contact structure to contact the conductive layer in the film stack of alternating conductive and dielectric layers.