Patents by Inventor Wenxi Zhou
Wenxi Zhou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12388036Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells. The second semiconductor structure includes a first peripheral circuit of the array of memory cells. The first peripheral circuit includes a first transistor. The first semiconductor structure or the second semiconductor structure further includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor. The first peripheral circuit and the second peripheral circuit are stacked over one another.Type: GrantFiled: September 21, 2021Date of Patent: August 12, 2025Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Liang Chen, Wei Liu, Yanhong Wang, Zhiliang Xia, Wenxi Zhou, Kun Zhang, Yuancheng Yang
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Patent number: 12388037Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second semiconductor layer is between the bonding interface and the second peripheral circuit.Type: GrantFiled: September 22, 2021Date of Patent: August 12, 2025Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Yanhong Wang, Wei Liu, Liang Chen, Zhiliang Xia, Wenxi Zhou, Kun Zhang, Yuancheng Yang
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Publication number: 20250254881Abstract: A memory, a controlling method thereof, a memory system and an electronic device are disclosed. The memory can include a semiconductor layer and a memory array disposed on the semiconductor layer. The memory array can include a plurality of memory strings connected with the same bit line. Each memory string can include a memory cell and a select cell connected on at least one side of the memory cell. The select cell can include a first kind of transistors with a first threshold voltage and a second kind of transistors with a second threshold voltage. The first kind of transistors can be connected with the second kind of transistors. The first threshold voltage can be different from the second threshold voltage. Different memory strings can be controlled to be on or off to realize selective controlling functions for a plurality of memory strings connected with the same bit line.Type: ApplicationFiled: April 22, 2025Publication date: August 7, 2025Inventors: Tao YANG, Dongxue Zhao, Wenxi Zhou, Zhiliang Xia
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Publication number: 20250246552Abstract: The present disclosure describes a three-dimensional (3D) memory device includes first and second memory arrays disposed on a semiconductor layer. The 3D memory device can also include a staircase structure disposed between the first and second memory arrays. The staircase structure includes first and second staircase regions. The first staircase region includes a first staircase structure that contains a first plurality of stairs descending in a first direction. The second staircase region includes a second staircase structure that contains a second plurality of stairs descending in a second direction. The 3D memory device can also include a contact region disposed between the first and second staircase regions. The contact region includes a plurality of contacts the extending through an insulating layer and into the semiconductor layer.Type: ApplicationFiled: March 19, 2025Publication date: July 31, 2025Inventors: Di WANG, Zhong ZHANG, Wenxi ZHOU
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THREE-DIMENSIONAL MEMORY DEVICE WITH DIVIDED DRAIN SELECT GATE LINES AND METHOD FOR FORMING THE SAME
Publication number: 20250240954Abstract: A memory device includes a stack structure over a substrate, a channel structure extending in the stack structure, and a dielectric layer over the channel structure. The dielectric layer includes a first material. The memory device may also include a drain-select gate (DSG) cut structure extending through the dielectric layer. The DSG cut structure includes a second material different from the first material.Type: ApplicationFiled: April 10, 2025Publication date: July 24, 2025Inventors: Di Wang, Yan Gu, Zhiliang Xia, Wenxi Zhou, Zongliang Huo -
Patent number: 12363898Abstract: Aspects of the disclosure provide a semiconductor device including a first die. The first die includes a first stack of layers including a semiconductor layer on a backside of the first die. A second stack of layers is formed that includes gate layers and first insulating layers alternatingly stacked on a face side of the first die. The face side is opposite to the backside. A vertical structure includes a first portion disposed in the first stack of layers and a second portion extending through the second stack of layers. The first portion has a different dimension than the second portion in a direction parallel to a main surface of the first die.Type: GrantFiled: January 5, 2022Date of Patent: July 15, 2025Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: LinChun Wu, Wenxi Zhou, Zhiliang Xia, ZongLiang Huo
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Publication number: 20250227928Abstract: Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a stack structure including interleaved conductive layers and dielectric layers along a first direction, a semiconductor layer over the stack structure, and a channel structure extending through the stack structure and in contact with the semiconductor layer. The channel structure includes a semiconductor channel extending along the first direction and a composite dielectric film surrounding the semiconductor channel. The semiconductor channel includes a first portion extending through at least one of the conductive layers. The at least one of the conductive layers is between the semiconductor layer and another of the conductive layers. The first portion includes a doped portion.Type: ApplicationFiled: March 31, 2025Publication date: July 10, 2025Inventors: Kun Zhang, Wenxi Zhou, Zhiliang Xia
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Publication number: 20250220908Abstract: In an example, a three-dimensional (3D) memory device includes a memory stack including interleaved conductive layers and dielectric layers, a channel structure extending vertically through the memory stack, a semiconductor layer over the memory stack and electrically connected to the channel structure, and a source contact over the memory stack and electrically connected to the semiconductor layer. The source contact and the memory stack are disposed on opposite sides of the semiconductor layer.Type: ApplicationFiled: March 14, 2025Publication date: July 3, 2025Inventors: Kun Zhang, Zhong Zhang, Lei Liu, Wenxi Zhou, Zhiliang Xia
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Publication number: 20250212407Abstract: A three-dimensional (3D) memory device includes a first region and a second region arranged along a first direction, a stack structure including interleaved conductive layers and dielectric layers along a second direction perpendicular to the first direction, a semiconductor layer located on a side of the stack structure along the second direction, a source contact structure at a first side of the semiconductor layer opposite to the stack structure, wherein the source contact structure is in contact with the semiconductor layer, a peripheral circuit at a second side of the semiconductor layer opposite to the first side of the semiconductor layer, and a supporting structure located in the second region and extending through the semiconductor layer along the second direction, wherein a material of the supporting structure is different from a material of the semiconductor layer.Type: ApplicationFiled: March 12, 2025Publication date: June 26, 2025Inventors: Cuicui Kong, Zhong Zhang, Linchun Wu, Kun Zhang, Wenxi Zhou
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Publication number: 20250201308Abstract: The present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes disposing an alternating dielectric stack over a substrate, wherein the alternating dielectric stack includes first dielectric layers and second dielectric layers alternatingly stacked on the substrate. The method also includes forming a channel structure penetrating through the alternating dielectric stack and extending into the substrate, wherein the channel structure includes a channel layer disposed on a sidewall of a memory film. The method further includes removing the substrate and a portion of the memory film that extends into the substrate to expose a portion of the channel layer; and disposing an array common source (ACS) on the exposed portion of the channel layer.Type: ApplicationFiled: March 5, 2025Publication date: June 19, 2025Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Linchun WU, Kun ZHANG, Wenxi ZHOU
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Publication number: 20250201306Abstract: The present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes sequentially forming a first and a second dielectric stacks on a substrate. The first dielectric stack includes a first and a second dielectric layers alternatingly stacked in a first direction perpendicular to the substrate. The second dielectric stack comprises a third and a fourth dielectric layers stacked in the first direction. The method further includes forming an etch-stop layer on the second dielectric stack and forming a gate line slit (GLS) trench spacer to cover a sidewall of the etch-stop layer. The method further includes replacing the fourth and the second dielectric layers with conductive layers through a GLS opening to form a top select gate (TSG) film stack and a film stack of alternating conductive and dielectric layers, respectively.Type: ApplicationFiled: March 3, 2025Publication date: June 19, 2025Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Di WANG, Wenxi ZHOU, Tingting ZHAO, Zhiliang XIA
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Patent number: 12327592Abstract: A method for performing an erasing operation on a memory device is provided. The memory device includes a bottom select gate, a plate line above the bottom select gate, a word line above the plate line, a pillar extending through the bottom select gate, the plate line, and the word line, a source line under the pillar, a drain cap above the pillar, and a bit line formed above the drain cap. A first positive voltage bias is applied to the bottom select gate. A second positive voltage bias is applied to the plate line. The first positive voltage bias to the bottom select gate is reduced. A negative voltage bias is applied to the source line.Type: GrantFiled: April 10, 2024Date of Patent: June 10, 2025Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: DongXue Zhao, Tao Yang, Yuancheng Yang, Lei Liu, Di Wang, Kun Zhang, Wenxi Zhou, Zhiliang Xia, Zongliang Huo
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Publication number: 20250183177Abstract: Embodiments of 3D memory structures and methods for forming the same are disclosed. The fabrication method includes disposing an alternating dielectric stack on a substrate, wherein the alternating dielectric stack having first and second dielectric layers alternatingly stacked on top of each other. Next, a plurality of contact openings can be formed in the alternating dielectric stack such that a dielectric layer pair can be exposed inside at least one of the plurality of contact openings. The method further includes forming a film stack of alternating conductive and dielectric layers by replacing the second dielectric layer with a conductive layer, and forming a contact structure to contact the conductive layer in the film stack of alternating conductive and dielectric layers.Type: ApplicationFiled: February 5, 2025Publication date: June 5, 2025Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhongwang SUN, Zhong ZHANG, Wenxi ZHOU, Lei LIU, Zhiliang XIA
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Patent number: 12322596Abstract: Methods for thermal treatment on a semiconductor device is disclosed. One method includes obtaining a pattern of a treatment area having amorphous silicon, aligning a laser beam with the treatment area, the laser beam in a focused laser spot having a spot area equal to or greater than the treatment area, and performing a laser anneal on the treatment area by emitting the laser beam towards the treatment area for a treatment period.Type: GrantFiled: December 1, 2021Date of Patent: June 3, 2025Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Kun Zhang, Lei Liu, Yuancheng Yang, Wenxi Zhou, Zhiliang Xia
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Publication number: 20250176160Abstract: Semiconductor devices, manufacturing methods thereof and memory systems are provided. In one aspect, a semiconductor device includes: channel structures. wherein at least one of the channel structures includes a first side portion and a second side portion arranged along a first direction and a connection portion connected to first end portions of the first side portion and the second side portion in a second direction; first dielectric layers located on surfaces of the first side portion and the second side portion that are opposite to each other; and gate layers located on surfaces of the first dielectric layers and extending along a third direction, wherein the first direction, the second direction, and the third direction intersect with each other.Type: ApplicationFiled: May 22, 2024Publication date: May 29, 2025Inventors: Yuancheng YANG, Lei LIU, Changzhi SUN, Wenxi ZHOU, ZhiLiang XIA, ZongLiang HUO
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Patent number: 12317496Abstract: A memory, a controlling method thereof, a memory system and an electronic device are disclosed. The memory can include a semiconductor layer and a memory array disposed on the semiconductor layer. The memory array can include a plurality of memory strings connected with the same bit line. Each memory string can include a memory cell and a select cell connected on at least one side of the memory cell. The select cell can include a first kind of transistors with a first threshold voltage and a second kind of transistors with a second threshold voltage. The first kind of transistors can be connected with the second kind of transistors. The first threshold voltage can be different from the second threshold voltage. Different memory strings can be controlled to be on or off to realize selective controlling functions for a plurality of memory strings connected with the same bit line.Type: GrantFiled: December 28, 2022Date of Patent: May 27, 2025Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Tao Yang, Dongxue Zhao, Wenxi Zhou, Zhiliang Xia
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Patent number: 12315802Abstract: A memory device includes a stack structure and a first beam structure. The memory device includes array regions and an intermediate region arranged between the array regions in a first lateral direction. The stack structure includes a first block and a second block arranged in a second lateral direction. Each of the first block and the second block includes a wall-structure region. In the intermediate region, the wall-structure regions of the first block and the second block are separated by a staircase structure. The first beam structure is located in the intermediate region and extends along the second lateral direction. The first beam structure is connected to the wall-structure regions of the first block and the second block. The first beam structure includes first dielectric layers and electrode layers that are alternately stacked.Type: GrantFiled: October 20, 2023Date of Patent: May 27, 2025Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Zhong Zhang, Kun Zhang, Wenxi Zhou, Zhiliang Xia
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Patent number: 12302573Abstract: A three-dimensional (3D) memory device includes a memory stack including interleaved conductive layers and dielectric layers over a first side of a second semiconductor layer, channel structures extending vertically through the memory stack and into the second semiconductor layer, source contacts in contact with a second side of the second semiconductor layer opposite to the first side; and a backside interconnect layer over the second side of the second semiconductor layer and including interlayer dielectric (ILD) layers and a source line mesh on the ILD layers. The source contacts are distributed on a side of the source line mesh. The source contacts extend through the ILD layers and into the second semiconductor layer.Type: GrantFiled: June 18, 2024Date of Patent: May 13, 2025Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Kun Zhang, Zhong Zhang, Lei Liu, Wenxi Zhou, Zhiliang Xia
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Three-dimensional memory device with divided drain select gate lines and method for forming the same
Patent number: 12302560Abstract: A memory device includes a stack structure over a substrate, a channel structure extending in the stack structure, and a dielectric layer over the channel structure. The dielectric layer includes a first material. The memory device may also include a drain-select gate (DSG) cut structure extending through the dielectric layer. The DSG cut structure includes a second material different from the first material.Type: GrantFiled: January 4, 2022Date of Patent: May 13, 2025Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Di Wang, Yan Gu, Zhiliang Xia, Wenxi Zhou, Zongliang Huo -
Patent number: 12300648Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and the second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second semiconductor layer is between the bonding interface and the second peripheral circuit.Type: GrantFiled: September 22, 2021Date of Patent: May 13, 2025Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Yuancheng Yang, Kun Zhang, Wenxi Zhou, Zhiliang Xia, Liang Chen, Yanhong Wang, Wei Liu