Abstract: A three-dimensional (3D) memory device includes a memory cell, a top contact coupled to the memory cell, and a bottom contact coupled to the memory cell. The memory cell can include a pillar, an insulating layer surrounding the pillar, a first gate contact coupled to a word line, a second gate contact coupled to a plate line, and an annular dielectric layer within a portion of the pillar. The annular dielectric layer can increase a retention time of electrical charge in the pillar. The 3D memory device can utilize dynamic flash memory (DFM), increase retention times, decrease refresh rates, increase a floating body effect, decrease manufacturing defects, decrease leakage current, decrease junction current, decrease power consumption, increase an upper limit of charge density in the pillar, dynamically adjust a length of the plate line, and decrease parasitic resistance.

Abstract: A semiconductor device is provided. The semiconductor device includes a first wafer having an array transistor formed therein, and a second wafer having a capacitor structure formed therein. The semiconductor device also includes a bonding interface formed between the first wafer and second wafer that includes a plurality of bonding structures. The bonding structures are configured to couple the array transistor to the capacitor structure to form a memory cell.

Abstract: Embodiments of three-dimensional memory devices are disclosed. A disclosed memory structure can comprises a memory cell, a bit line contact coupled to the memory cell, a bit line coupled to the bit line contact, a source line contact coupled to the memory cell, and a source line coupled to the source line contact. The memory cell comprises a cylindrical body having a cylindrical shape, an insulating layer surrounding the cylindrical body, a word line contact surrounding a first portion of the insulating layer, the word line contact coupled to a word line, and a plurality of plate line contact segments surrounding a second portion of the insulating layer, the plurality of plate line contact segments coupled to a common plate line.

Abstract: In a method for fabricating a semiconductor device, an initial stack of sacrificial word line layers and insulating layers is formed over a substrate of the semiconductor device. The sacrificial word line layers and the insulating layers are disposed over the substrate alternately. A first staircase is formed in a first staircase region of a connection region of the initial stack. A second staircase is formed in a second staircase region of the connection region of the initial stack. The connection region of the initial stack includes a separation region between the first and second staircases, and the connection region is positioned between array regions of the initial stack at opposing sides of the initial stack.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a doped region of a substrate. The doped region includes dopants of a first type. The 3D memory device also includes a semiconductor layer on the doped region. The semiconductor layer includes dopants of a second type. The first type and the second type are different from each other. The 3D memory device also includes a memory stack having interleaved conductive layers and dielectric layers on the semiconductor layer. The 3D memory device further includes a channel structure extending vertically through the memory stack and the semiconductor layer into the doped region, a semiconductor plug extending vertically into the doped region, the semiconductor plug comprising dopants of the second type, and a source contact structure extending vertically through the memory stack to be in contact with the semiconductor plug.

Abstract: Memory device includes a bottom-select-gate (BSG) structure. Cut slits are formed vertically through the BSG structure, on a substrate. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. The gate-line slits include a first gate-line slit between first and second finger regions, the first gate-line slit including gate-line sub-slits. The cut slits include a first cut-slit, formed in the second finger region and connecting to a gate-line sub-slit to define a BSG in a first portion of the second finger region. The BSG in the first portion of the second finger region is electrically connected to cell strings in the first finger region through an inter portion between the one gate-line sub-slit and an adjacent gate-line sub-slit.

Abstract: In an example, a three-dimensional (3D) memory device includes a memory array structure including a first and a second memory array structures, a staircase structure between the first and a second memory array structures in a first lateral direction and including a first and a second staircase zones, and a bridge structure between the first and second staircase zones in a second lateral direction perpendicular to the first lateral direction. Each of the first and second staircase zones includes first and second sub-staircases arranged alternately. Each first sub-staircase includes ascending stairs at different depths. Each second sub-staircase includes descending stairs at different depths. At least one stair in each of the first and second sub-staircases is connected to at least one of the first and second memory array structures through the bridge structure.

Abstract: A semiconductor device is provided. The semiconductor device includes a first wafer having an array transistor formed therein, and a second wafer having a capacitor structure formed therein. The semiconductor device also includes a bonding interface formed between the first wafer and second wafer that includes a plurality of bonding structures. The bonding structures are configured to couple the array transistor to the capacitor structure to form a memory cell.

Abstract: In an example of the present disclosure, a three-dimensional (3D) memory device includes a memory array structure and a staircase structure dividing the memory array structure into a first memory array structure and a second memory array structure along a lateral direction. The staircase structure includes a plurality of stairs, and a bridge structure in contact with the first memory array structure and the second memory array structure. A stair of the plurality of stairs includes a conductor portion on a top surface of the stair and electrically connected to the bridge structure, and a dielectric portion at a same level and in contact with the conductor portion. The stair is electrically connected to at least one of the first memory array structure and the second memory array structure. The conductor portion includes a portion overlapping with an immediately-upper stair and in contact with the dielectric portion and the bridge structure.

Abstract: Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes depositing a cover layer over a substrate, depositing a sacrificial layer over the cover layer, depositing a layer stack over the sacrificial layer, forming a channel layer extending through the layer stack and the sacrificial layer, performing a first epitaxial growth to deposit a first epitaxial layer on a side portion of the channel layer that is close to the substrate, removing the cover layer, and performing a second epitaxial growth to simultaneously thicken the first epitaxial layer and deposit a second epitaxial layer on the substrate. The layer stack includes first stack layers and second stack layers that are alternately stacked.

Abstract: A three-dimensional (3D) memory device includes a stack structure including interleaved first conductive layers and first dielectric layers, a channel structure extending through the stack structure along a first direction in contact with a first semiconductor layer at a bottom portion of the channel structure, and a slit structure extending through the stack structure along the first direction. The slit structure includes a slit core, and a second dielectric layer surrounding the slit core. A first width of the second dielectric layer near the first semiconductor layer is larger than a second width of the second dielectric layer away from the first semiconductor layer.

Abstract: Memory device includes a bottom-select-gate (BSG) structure formed on a substrate. Cut slits are formed vertically through the BSG structure. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. The gate-line slits include a first gate-line slit between first and second finger regions, the first gate-line slit including gate-line sub-slits. The cut slits include a first cut-slit, formed in the second finger region and connecting to a gate-line sub-slit to define a BSG in a first portion of the second finger region. The BSG in the first portion of the second finger region is electrically connected to cell strings in the first finger region through an inter portion between the one gate-line sub-slit and an adjacent gate-line sub-slit.

Abstract: In an example of the present disclosure, 3D memory device includes a memory array structure and a staircase structure dividing the memory array structure into a first memory array structure and a second memory array structure along a lateral direction. The staircase structure includes a plurality of stairs, and a bridge structure in contact with the first memory array structure and the second memory array structure. A stair of the plurality of stairs includes a conductor portion on a top surface of the stair and electrically connected to the bridge structure, and a dielectric portion at a same level and in contact with the conductor portion. The stair is electrically connected to at least one of the first memory array structure and the second memory array structure. The conductor portion includes a portion overlapping with an immediately-upper stair and in contact with the dielectric portion and the bridge structure.

Abstract: Embodiments of 3D memory devices having staircase structures and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory array structure and a staircase structure in an intermediate of the memory array structure and laterally dividing the memory array structure into a first memory array structure and a second memory array structure. The staircase structure includes a first staircase zone and a bridge structure connecting the first memory array structure and the second memory array structure. The first staircase zone includes a first pair of staircases facing each other in a first lateral direction and at different depths. Each staircase includes a plurality of stairs. At least one stair in the first pair of staircases is electrically connected to at least one of the first memory array structure and the second memory array structure through the bridge structure.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device comprises forming a channel structure extending vertically through a memory stack into a semiconductor layer on a substrate. The memory stack comprises interleaved stack conductive layers and stack dielectric layers. The method further comprises forming an insulating structure in an opening extending vertically through the memory stack and at a distance away from the channel structure, and comprising a dielectric layer doped with at least one of hydrogen or an isotope of hydrogen.

Abstract: The present disclosure provides a method for forming a three-dimensional memory device. The method includes disposing an alternating dielectric stack on a substrate in a first direction perpendicular to the substrate; and forming a staircase structure and a dividing wall in the alternating dielectric stack. The staircase structure and the dividing wall extend in a second direction parallel to the substrate, and the dividing wall is adjacent to the staircase structure. The method also includes forming, sequentially on the staircase structure, a first barrier layer and a second barrier layer different from the first barrier layer. The method further includes forming a gate line slit (GLS) opening in the dividing wall. The GLS opening penetrates through the alternating dielectric stack in the first direction and is distant from the second barrier layer in a third direction that is parallel to the substrate and is perpendicular to the second direction.

Abstract: A memory device includes a stack structure over a substrate, a channel structure extending in the stack structure, and a dielectric layer over the channel structure. The dielectric layer includes a first material. The memory device may also include a drain-select gate (DSG) cut structure extending through the dielectric layer. The DSG cut structure includes a second material different from the first material.

Abstract: The present disclosure is directed to a memory structure including a staircase structure. The staircase structure can include a bottom select gate, a plate line formed above the bottom select gate, and a word line formed above the plate line. The pillar can extend through the bottom select gate, the plate line, and the word line. The memory structure can also include a source structure formed under the pillar and a drain cap formed above the pillar. The memory structure can further include a bit line formed above the drain cap.

Abstract: Embodiments of 3D memory devices having staircase structures and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory array structure and a staircase structure in an intermediate of the memory array structure and laterally dividing the memory array structure into first and second memory array structures. The staircase structure includes a first staircase zone and a bridge structure connecting the first and second memory array structures. The first staircase zone includes a first pair of staircases facing each other in a first lateral direction and at different depths. Each staircase includes a plurality of stairs. Each staircase includes divisions in a second lateral direction perpendicular to the first lateral direction at different depths. At least one stair in the first pair of staircases is electrically connected to at least one of the first and second memory array structures through the bridge structure.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes: a memory stack comprising interleaved conductive layers and dielectric layers; a plurality of channel structures extending vertically through the memory stack; a plurality of channel local contacts each located above and in contact with a corresponding one of the plurality of channel structures, and having a metal material; and a slit structure extending vertically through the memory stack and laterally along a first direction to separate the plurality of channel structures. The slit structure comprises a contact. The contact comprises a first contact portion having a semiconductor material and a second contact portion above the first contact portion and having the metal material. An upper end of the second contact portion and upper ends of the plurality of channel local contacts are coplanar.