Abstract: Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, the memory device includes a stack structure having interleaved a plurality of sacrificial layers and a plurality of dielectric layers over a substrate along a vertical direction. The memory device also includes a channel structure extending in the stack structure along the vertical direction. A thickness of at least one of the plurality of sacrificial layers is nominally proportional to a width of the channel structure at the same depth. A thickness of at least one of the plurality of dielectric layers is nominally inversely proportional to a width of the channel structure at the same depth.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack comprising interleaved conductive layers and dielectric layers, a plurality of semiconductor layers contacted with each other and located adjacent to the memory stack, a plurality of channel structures each extending vertically through the memory stack and at least one of the semiconductor layers, a source contact in contact with at least one of the semiconductor layers, and a contact pad located on one side of the semiconductor layers that are away from the memory stack.

Abstract: The present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes disposing an alternating dielectric stack over a substrate, wherein the alternating dielectric stack includes first dielectric layers and second dielectric layers alternatingly stacked on the substrate. The method also includes forming a channel structure penetrating through the alternating dielectric stack and extending into the substrate, wherein the channel structure includes a channel layer disposed on a sidewall of a memory film. The method further includes removing the substrate and a portion of the memory film that extends into the substrate to expose a portion of the channel layer; and disposing an array common source (ACS) on the exposed portion of the channel layer.

Abstract: Three-dimensional memory devices and fabricating methods therefore are disclosed. The memory device can comprise a stack structure comprising a plurality of gate layers, a plurality of first insulating layers, and a plurality of second insulating layers. The stack structure has a staircase region comprising a plurality of stair structures. Each stair structure comprises a first portion of the stair structure comprising one gate layer and a first portion of one first insulating layer, and a second portion of the stair structure comprising a second portion of the one first insulating layer and a second insulating layer. The memory device can further comprise at least one contact structure each located on a top surface of one of the plurality of stair structures, and at least one contact portion in contact with the at least one contact structure.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, a first semiconductor layer above the memory stack, a second semiconductor layer above and in contact with the first semiconductor layer, a plurality of channel structures each extending vertically through the memory stack and the first semiconductor layer, and a source contact above the memory stack and in contact with the second semiconductor layer.

Abstract: Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a stack structure including interleaved conductive layers and dielectric layers, a channel structure extending through the stack structure, and a doped semiconductor layer including a plate and a plug extending from the plate into the channel structure. The channel structure includes a memory film and a semiconductor channel. The semiconductor channel includes a doped portion, and a part of the doped portion of the semiconductor channel extends beyond the stack structure in a first direction. The doped portion of the semiconductor channel circumscribes the plug of the doped semiconductor layer.

Abstract: Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a stack structure including interleaved conductive layers and stack dielectric layers, a channel structure extending through the stack structure, and a doped semiconductor layer. The channel structure includes a memory film and a semiconductor channel. The semiconductor channel includes a doped portion and an undoped portion. A part of the doped portion of the semiconductor channel extends beyond the stack structure in a first direction. A part of the doped semiconductor layer is in contact with a sidewall of the part of the doped portion of the semiconductor channel that extends beyond the stack structure.

Abstract: Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a stack structure including interleaved conductive layers and dielectric layers, a doped semiconductor layer, and a channel structure extending through the stack structure and in contact with the doped semiconductor layer. The channel structure includes a composite dielectric film and a semiconductor channel along a first direction. The composite dielectric film includes a gate dielectric portion and a memory portion along a second direction perpendicular to the first direction. A part of the gate dielectric portion faces, along the first direction, one of the conductive layers that is closest to the doped semiconductor layer.

Abstract: Embodiments of 3D memory devices having staircase structures and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory array structure and a staircase structure in an intermediate of the memory array structure. The staircase structure includes a plurality of stairs extending along the lateral direction, and a bridge structure in contact with the first memory array structure and the second memory array structure. The plurality of stairs includes a stair above one or more dielectric pairs The stair includes a conductor portion on a top surface of the stair and in contact with and electrically connected to the bridge structure, and is electrically connected to at least one of a first memory array structure and a second memory array structure of the memory array structure through the bridge structure. Along a second lateral direction, a width of the conductor portion is unchanged.

Abstract: A three-dimensional (3D) memory device includes a core array region and a staircase region adjacent to the core array region. The core array region includes a memory stack having a plurality of conductor layers and a plurality of dielectric layers stacked alternatingly, a first semiconductor layer disposed over the memory stack, and a channel structure extending through the memory stack and the first semiconductor layer. The staircase region includes a staircase structure, a supporting structure disposed over the staircase structure, and a plurality of contacts contacting the plurality of conductor layers in the staircase structure. The first semiconductor layer overlaps the core array region in a plan view of the 3D memory device and the supporting structure overlaps the staircase region in the plan view of the 3D memory device.

Abstract: The present disclosure describes a three-dimensional (3D) memory device includes first and second memory arrays disposed on a semiconductor layer. The 3D memory device can also include a staircase structure disposed between the first and second memory arrays. The staircase structure includes first and second staircase regions. The first staircase region includes a first staircase structure that contains a first plurality of stairs descending in a first direction. The second staircase region includes a second staircase structure that contains a second plurality of stairs descending in a second direction. The 3D memory device can also include a contact region disposed between the first and second staircase regions. The contact region includes a plurality of contacts the extending through an insulating layer and into the semiconductor layer.

Abstract: Aspects of the disclosure provide a method for data erase in a memory device. The method includes providing first erase carriers from a body portion for the memory cell string, during an erase operation in a memory cell string. The first erase carriers flow in a first direction from a source side of the memory cell string to a drain side of the memory cell string. Further, the method includes providing second erase carriers from a junction at the drain side of the memory cell string. The second erase carriers flow in a second direction from the drain side of the memory cell string to the source side of the memory cell string. Then, the method includes injecting the first erase carriers and the second erase carriers to charge storage portions of the memory cells in the memory cell string.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a stack of word line layers and insulating layers that are stacked alternatingly over the substrate, and channel structures formed in a first array region and a second array region of the stack. The first array region and the second array region are positioned at opposing sides of the stack. A first staircase is formed in a connection region of the stack over the substrate, where the connection region is arranged between the first and second array regions. A second staircase is formed in the connection region of the stack over the substrate, and the connection region in the stack includes a separation region between the first and second staircases.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A stop layer, a first polysilicon layer, a sacrificial layer, a second polysilicon layer, and a dielectric stack are sequentially formed at a first side of a substrate. A channel structure extending vertically through the dielectric stack, the second polysilicon layer, the sacrificial layer, and the first polysilicon layer, stopping at the stop layer, is formed. An opening extending vertically through the dielectric stack and the second polysilicon layer, stopping at the sacrificial layer to expose part of the sacrificial layer, is formed. The sacrificial layer is replaced, through the opening, with a third polysilicon layer between the first and second polysilicon layers. The substrate is removed from a second side opposite to the first side of the substrate, stopping at the stop layer.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A peripheral circuit is formed on a first substrate. A first semiconductor layer is formed on a second substrate. A supporting structure and a second semiconductor layer coplanar with the supporting structure are formed on the first semiconductor layer. A memory stack is formed above the supporting structure and the second semiconductor layer. The memory stack has a staircase region overlapping the supporting structure. A channel structure extending vertically through the memory stack and the second semiconductor layer into the first semiconductor layer is formed. The first substrate and the second substrate are bonded in a face-to-face manner.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a stack of word line layers and insulating layers that are stacked alternatingly over the substrate, and channel structures formed in a first array region and a second array region of the stack. The first array region and the second array region are positioned at opposing sides of the stack. A first staircase is formed in a connection region of the stack over the substrate, where the connection region is arranged between the first and second array regions. A second staircase is formed in the connection region of the stack over the substrate, and the connection region in the stack includes a separation region between the first and second staircases.

Abstract: A 3D memory device includes a memory stack including interleaved stack conductive layers and stack dielectric layers, a semiconductor layer, and a channel structure extending vertically through the memory stack into the semiconductor layer. A first lateral dimension of a first portion of the channel structure facing the semiconductor layer is greater than a second lateral dimension of a second portion of the channel structure facing the memory stack. The channel structure includes a memory film and a semiconductor channel A first doping concentration of part of the semiconductor channel in the first portion of the channel structure is greater than a second doping concentration of part of the semiconductor channel in the second portion of the channel structure.

Abstract: A 3D memory device includes a memory stack and a support structure. The memory stack, on a substrate, includes a core region and a non-core region neighboring the core region. The support structure extends in the non-core region and into the substrate. The support structure includes a first support portion and a second support portion over the first support portion. The first support portion has a stiffness higher than the second support portion.

Abstract: Embodiments of 3D memory devices having a concentric staircase structure and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory array structure and a concentric staircase structure in an intermediate of the memory array structure. The concentric staircase structure includes a plurality of concentric zones in a radial direction in a plan view. Each of the plurality of concentric zones includes a plurality of stairs in a tangential direction in the plan view.

Abstract: Embodiments of 3D memory structures and methods for forming the same are disclosed. The fabrication method includes disposing an alternating dielectric stack on a substrate, wherein the alternating dielectric stack having first and second dielectric layers alternatingly stacked on top of each other. Next, a plurality of contact openings can be formed in the alternating dielectric stack such that a dielectric layer pair can be exposed inside at least one of the plurality of contact openings. The method further includes forming a film stack of alternating conductive and dielectric layers by replacing the second dielectric layer with a conductive layer, and forming a contact structure to contact the conductive layer in the film stack of alternating conductive and dielectric layers.