Abstract: A method of fabricating a semiconductor device is described. The method includes forming a nanosheet stack on a substrate, the nanosheet stack includes nanosheet channel layers. A gate is formed around the nanosheet channel layers of the nanosheet stack. A strained material is formed along a sidewall surface of the gate. The strained material is configured to create strain in the nanosheet channel layers of the nanosheet stack.

Abstract: Semiconductor devices and methods of forming the same include etching a stack of alternating channel and sacrificial layers to form a fin. The etch depth is controlled by a signal layer embedded in a substrate under the stack. Source and drain regions are formed on ends of the channel layers. The sacrificial layers are etched away and a gate stack is formed over and between the channel layers.

Abstract: A method for manufacturing a semiconductor device includes forming a fin on a semiconductor substrate. In the method, a bottom source/drain region is formed between the fin and the semiconductor substrate, and a top source/drain region is formed on the fin. The method further includes forming a cap layer covering part of a top surface of the top source/drain region. A portion of the top source/drain region and an underlying portion of the fin not covered by the cap layer are removed. The removal exposes a portion of the bottom source/drain region. A dielectric spacer is formed on a side of the fin adjacent the exposed portion of the bottom source/drain region, and extends onto a side of the top source/drain region. A bottom source/drain contact is formed on the exposed portion of the bottom source/drain region and on the dielectric spacer.

Abstract: A method for forming a semiconductor device is disclosed. The method includes receiving a substrate stack including at least one semiconductor fin, the substrate stack including: a bottom source/drain epi region directly below the semiconductor fin; a vertical gate structure directly above the bottom source/drain epi region and in contact with the semiconductor fin; a first inter-layer dielectric in contact with a sidewall of the vertical gate structure; and a second interlayer-layer dielectric directly above and contacting a top surface of the first inter-layer dielectric. The method further including: etching a top region of the semiconductor fin and the gate structure thereby creating a recess directly above the top region of the semiconductor fin and the vertical gate structure; and forming in the recess a top source/drain epi region directly above, and contacting, a top surface of the semiconductor fin. A novel semiconductor device structure is also disclosed.

Abstract: Embodiments of the invention are directed to method of fabricating a semiconductor device. A non-limiting embodiment of the method includes performing fabrication operations to form a nanosheet field effect transistor (FET) device on a substrate, wherein the fabrication operations include forming gate spacers along a gate region of the nanosheet FET device, wherein each of the gate spacers comprises an upper segment and a lower segment.

Abstract: A method of forming a vertical fin field effect transistor device is provided. The method includes forming a vertical fin and fin template on a bottom source/drain layer, wherein the fin template is on the vertical fin. The method further includes forming a gate structure on the vertical fin and fin template, and forming a top spacer layer on the gate structure. The method further includes removing the fin template to form an opening in the top spacer layer, and removing a portion of a gate electrode of the gate structure to form a cavity; and removing a portion of a gate dielectric layer of the gate structure to form a groove around the vertical fin.

Abstract: A method for manufacturing a semiconductor device includes forming a stacked configuration of a plurality of silicon germanium layers and a plurality of silicon layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a silicon layer stacked on a silicon germanium layer, patterning the stacked configuration into a plurality of patterned stacks spaced apart from each other, and etching exposed sides of the plurality of silicon germanium layers to remove portions of the silicon germanium layers from lateral sides of each of the plurality of silicon germanium layers, wherein a concentration of germanium is varied between each of the plurality of silicon germanium layers to compensate for variations in etching rates between the plurality of silicon germanium layers to result in remaining portions of each of the plurality of silicon germanium layers having the same or substantially the same width as each other.

Abstract: A method of forming fin field effect devices is provided. The method includes forming a plurality of vertical fins on a substrate. The method further includes forming a dielectric pillar on the substrate between two adjacent vertical fins, wherein at least one of the vertical fins is on a first region of the substrate, and at least one of the vertical fins is on a second region of the substrate. The method further includes growing a bottom source/drain layer on the first region of the substrate and the second region of the substrate. The method further includes depositing a bottom spacer layer on the bottom source/drain layer, and a filler layer on the bottom spacer layer. The method further includes forming a cover block on the first region of the substrate, and removing the portion of the filler layer on the second region of the substrate.

Abstract: The present invention provides PCM devices with gradual SET and RESET characteristics. In one aspect, a method of forming a PCM computing device includes: forming word lines and an insulating hardmask cap on a substrate; forming a PCM material over the word lines, having a tapered thickness; and forming bit lines over the PCM material, the insulating hardmask cap, and the word lines, wherein the tapered thickness of the PCM material varies gradually between the word lines and the bit lines. The tapered thickness can be formed by depositing a non-conformal layer of the PCM material or by depositing a conformal layer and then tapering the PCM material using a directional etch. A PCM device is also provided.

Abstract: Semiconductor devices and methods are provided to fabricate FET devices. For example, a semiconductor device can include a functional gate structure on a channel region of a fin structure; and a source/drain region on each side of the functional gate structure. The functional gate structure has an insulator material abutting a portion of the sidewalls of the functional gate structure and the source drain region and the top surface of the fin. The functional gate structure further includes a dielectric top layer. The dielectric top layer seals an air gap between the top surface of the insulator material and the dielectric top layer.

Abstract: A technique relates to a semiconductor device. A first vertical fin is formed with a first gate stack and a second vertical fin with a second gate stack. The second vertical fin has a hardmask on top. The first vertical fin is adjacent to a first bottom source or drain (S/D) region and the second vertical fin is adjacent to a second bottom S/D region. The first gate stack is reduced to a first gate length and the second gate stack to a second gate length, the second gate length being greater than the first gate length because of the hardmask. The hardmask is removed. A first top S/D region is adjacent to the first vertical fin and a second top S/D region is adjacent to the second vertical fin.

Abstract: Embodiments of the invention are directed to a method of fabricating a field effect transistor device, wherein the fabrication operations include forming a channel region over a substrate, forming a gate region over a top surface and along sidewalls of the channel region, and forming a source or drain (S/D) region over the substrate. A bottom encapsulated air-gap is formed over the substrate, and a first portion of the bottom encapsulated air-gap is positioned between the gate region and the S/D region. The first portion of the bottom encapsulated air-gap is further positioned below the top surface of the channel region.

Abstract: A method of forming a fin field effect transistor is provided. The method includes forming an elevated substrate tier on a substrate, and forming a fin mesa on the elevated substrate tier with a fin template layer on the fin mesa, wherein the elevated substrate tier is laterally larger than the fin mesa and fin template layer. The method includes forming a fill layer on the substrate, wherein the fill layer surrounds the fin mesa, elevated substrate tier, and fin template layer, forming a plurality of fin masks on the fill layer and fin template layer, and removing portions of the fill layer, fin template layer, and fin mesa to form a plurality of dummy fins from the fill layer, one or more vertical fins from the fin mesa, and a dummy fin portion on opposite ends of each of the one or more vertical fins from the fill layer.

Abstract: A method of forming fin field effect devices is provided. The method includes forming a plurality of vertical fins on a substrate. The method further includes forming a dielectric pillar on the substrate between two adjacent vertical fins, wherein at least one of the vertical fins is on a first region of the substrate, and at least one of the vertical fins is on a second region of the substrate. The method further includes growing a bottom source/drain layer on the first region of the substrate and the second region of the substrate. The method further includes depositing a bottom spacer layer on the bottom source/drain layer, and a filler layer on the bottom spacer layer. The method further includes forming a cover block on the first region of the substrate, and removing the portion of the filler layer on the second region of the substrate.

Abstract: A method for fabricating a semiconductor device includes forming a semiconductor structure including a substrate, a first vertical fin and a second vertical fin longitudinally spaced from the first vertical fin with each of the first and second vertical fin having a hardmask cap, and a bottom spacer layer on the substrate. The method further includes forming first and second bottom source/drains within the substrate respectively beneath the first and second vertical fins, forming first and second top source/drains respectively on the first and second vertical fins, forming a vertical oxide pillar between the first and second vertical fins, removing a portion of the oxide pillar to reduce a cross-sectional dimension to define a lower recessed region, and depositing a metal gate material about the first and second vertical fins wherein portions of the metal gate material are disposed within the recessed region of the oxide pillar.

Abstract: Transistors and methods of forming the same include forming a fin that has an active layer between two sacrificial layers. Material is etched away from the two sacrificial layers in a region of the fin. A gate stack is formed around the active layer in the region. The active layer is etched after forming the gate stack to form a quantum dot.

Abstract: A method of forming a vertical fin field effect transistor with a self-aligned gate structure, comprising forming a plurality of vertical fins on a substrate, forming gate dielectric layers on opposite sidewalls of each vertical fin, forming a gate fill layer between the vertical fins, forming a fin-cut mask layer on the gate fill layer, forming one or more fin-cut mask trench(es) in the fin-cut mask layer, and removing portions of the gate fill layer and vertical fins not covered by the fin-cut mask layer to form one or more fin trench(es), and two or more vertical fin segments from each of the plurality of vertical fins, having a separation distance, D1, between two vertical fin segments.

Abstract: The present invention provides PCM devices with gradual SET and RESET characteristics. In one aspect, a method of forming a PCM computing device includes: forming word lines and an insulating hardmask cap on a substrate; forming a PCM material over the word lines, having a tapered thickness; and forming bit lines over the PCM material, the insulating hardmask cap, and the word lines, wherein the tapered thickness of the PCM material varies gradually between the word lines and the bit lines. The tapered thickness can be formed by depositing a non-conformal layer of the PCM material or by depositing a conformal layer and then tapering the PCM material using a directional etch. A PCM device is also provided.

Abstract: Devices and methods are provided for forming single diffusion break isolation structures for integrated circuit devices including gate-all-around FET devices such as nanosheet FET devices and nanowire FET devices. For example, a semiconductor integrated circuit device includes first and second gate-all-around field-effect transistor devices disposed in first and second device regions, respectively, of a semiconductor substrate. A single diffusion break isolation structure is disposed between the first and second device regions. The single diffusion break isolation structure includes a dummy gate structure disposed on the semiconductor substrate between a first source/drain layer of the first gate-all-around field-effect transistor device and a second source/drain layer of the second gate all-around field-effect transistor device. The single diffusion break isolation structure is configured to electrically isolate the first and second source/drain layers.

Abstract: A method for forming a semiconductor device comprises forming a fin on a substrate and forming a sacrificial gate over a channel region of the fin. A hydrogen terminated surface is formed on sidewalls of the sacrificial gate, and a spacer is deposited on the hydrogen terminated surface of the sacrificial gate. An insulator layer is formed over portions of the fin. The sacrificial gate is removed to expose the channel region of the fin, and a gate stack is formed over the channel region of the fin.