Abstract: An opportunistic storage service, or system, identifies currently unused storage capacity on a plurality of physical storage components of computing devices dispersed throughout a provider network. In some embodiments, the currently unused storage capacity is provisioned as primary storage, but is not currently being used to store primary storage data. The opportunistic storage service advertises at least a portion of the currently unused storage capacity as opportunistic storage capacity and provisions the opportunistic storage capacity subject to revocation if additional storage capacity of the physical storage components is needed to store primary storage data to fulfill a primary storage commitment.

Abstract: An opportunistic storage service, or system, identifies currently unused storage capacity on a plurality of physical storage components of computing devices dispersed throughout a provider network. In some embodiments, the currently unused storage capacity is provisioned as primary storage, but is not currently being used to store primary storage data. The opportunistic storage service advertises at least a portion of the currently unused storage capacity as opportunistic storage capacity and provisions the opportunistic storage capacity subject to revocation if additional storage capacity of the physical storage components is needed to store primary storage data to fulfill a primary storage commitment.

Abstract: An opportunistic storage service, or system, identifies currently unused storage capacity on a plurality of physical storage components of computing devices dispersed throughout a provider network. In some embodiments, the currently unused storage capacity is provisioned as primary storage, but is not currently being used to store primary storage data. The opportunistic storage service advertises at least a portion of the currently unused storage capacity as opportunistic storage capacity and provisions the opportunistic storage capacity subject to revocation if additional storage capacity of the physical storage components is needed to store primary storage data to fulfill a primary storage commitment.

Abstract: The following description is directed to managing a nonvolatile medium. The nonvolatile medium can be organized as a plurality of storage units. In one example, a method can include measuring read latencies for the individual storage units of the nonvolatile medium. A probability distribution of future read latencies for the nonvolatile medium can be estimated based on the measured read latencies for the individual storage units of the nonvolatile medium. Information can be moved from a particular storage unit of the nonvolatile medium to a different storage unit of the nonvolatile medium based on the estimated probability distribution of future read latencies for the nonvolatile medium.

Abstract: An adaptive read algorithm for accessing information stored on a nonvolatile medium. The nonvolatile medium can be organized as a plurality of storage units. A method of servicing a read request to the nonvolatile medium can include recording a history of read-retries for read requests to individual storage units of the nonvolatile medium. The method can include adapting a read algorithm for a read request to a particular storage unit based on the history of the read-retries for the read requests to the individual storage units of the nonvolatile medium.

Abstract: Techniques for efficiently programming non-volatile storage are disclosed. A second page of data may efficiently be programmed into memory cells that already store a first page. Data may be efficiently transferred from single bit cells to multi-bit cells. Memory cells are read using at least two different read levels. The results are compared to determine a count how many memory cells showed a different result between the two reads. If the count is less than a threshold, then data from the memory cells is stored into a set of data latches without attempting to correct for misreads. If the count is not less than the threshold, then data from the memory cells is stored into the set of data latches with attempting to correct for misreads. A programming operation may be performed based on the data stored in the set of data latches.

Abstract: The various implementations described herein include systems, methods and/or devices used to enable adaptive verify voltage adjustment in memory devices. The method includes: (1) in conjunction with decoding data read from non-volatile memory in the non-volatile memory system, determining a plurality of error parameters, (2) determining, in accordance with the plurality of error parameters, a verify adjustment signal, (3) determining whether a verify trigger event has occurred, (4) in accordance with a determination that a verify trigger event has occurred, adjusting a verify voltage in accordance with the verify adjustment signal, and (5) performing data write operations to write data to non-volatile memory in the non-volatile memory system using the adjusted verify voltage to verify the data written using the data write operations.

Abstract: Techniques for efficiently programming non-volatile storage are disclosed. A second page of data may efficiently be programmed into memory cells that already store a first page. Data may be efficiently transferred from single bit cells to multi-bit cells. Memory cells are read using at least two different read levels. The results are compared to determine a count how many memory cells showed a different result between the two reads. If the count is less than a threshold, then data from the memory cells is stored into a set of data latches without attempting to correct for misreads. If the count is not less than the threshold, then data from the memory cells is stored into the set of data latches with attempting to correct for misreads. A programming operation may be performed based on the data stored in the set of data latches.

Abstract: Methods, devices, and systems associated with multilevel phase change memory cells are described herein. One or more embodiments of the present disclosure include operating a phase change memory device by placing a phase change memory cell in a reset state and applying a selected programming pulse to the phase change memory cell in order to program the cell to one of a number of intermediate states between the reset state and a set state associated with the cell. The selected programming pulse includes an uppermost magnitude applied for a particular duration, the particular duration depending on to which one of the number of intermediate states the memory cell is to be programmed.

Abstract: Techniques are disclosed herein for performing an Internal Data Load (IDL) to sense non-volatile storage elements. Read pass voltages that are applied to the two neighbor word lines to a selected word line may be adjusted to result in a more accurate IDL. The read pass voltage for one neighbor may be increased by some delta voltage, whereas the read pass voltage for the other neighbor may be decreased by the same delta voltage. In one aspect, programming of an upper page of data into a word line that neighbors a target word line is halted to allow lower page data in the target memory cells to be read using an IDL and preserved in data latches while programming the upper page in the neighbor word completes. Preservation of the lower page data provides for a cleaner lower page when later programming the upper page into the target memory cells.

Abstract: Techniques for efficiently programming non-volatile storage are disclosed. A second page of data may efficiently be programmed into memory cells that already store a first page. Data may be efficiently transferred from single bit cells to multi-bit cells. Memory cells are read using at least two different read levels. The results are compared to determine a count how many memory cells showed a different result between the two reads. If the count is less than a threshold, then data from the memory cells is stored into a set of data latches without attempting to correct for misreads. If the count is not less than the threshold, then data from the memory cells is stored into the set of data latches with attempting to correct for misreads. A programming operation may be performed based on the data stored in the set of data latches.

Abstract: A system for reducing read disturb on edge word lines in non-volatile storage is disclosed. In one embodiment, the memory cells on edge word lines are programmed using a series of pulses that have an initial magnitude and step size between pulses that are lower than for memory cells on word lines that are not edge word lines. Additionally, when reading memory cells on word lines that are not edge word lines, the edge word lines receive a lower pass voltage than the default pass voltage applied to other unselected word lines. In another embodiment. the system applies a higher than normal bias on a neighboring word lines when reading memory cells on an edge word line.

Abstract: Techniques are disclosed herein for performing an Internal Data Load (IDL) to sense non-volatile storage elements. Read pass voltages that are applied to the two neighbor word lines to a selected word line may be adjusted to result in a more accurate IDL. The read pass voltage for one neighbor may be increased by some delta voltage, whereas the read pass voltage for the other neighbor may be decreased by the same delta voltage. In one aspect, programming of an upper page of data into a word line that neighbors a target word line is halted to allow lower page data in the target memory cells to be read using an IDL and preserved in data latches while programming the upper page in the neighbor word completes. Preservation of the lower page data provides for a cleaner lower page when later programming the upper page into the target memory cells.

Abstract: Techniques are disclosed herein for performing an Internal Data Load (IDL) to sense non-volatile storage elements. Read pass voltages that are applied to the two neighbor word lines to a selected word line may be adjusted to result in a more accurate IDL. The read pass voltage for one neighbor may be increased by some delta voltage, whereas the read pass voltage for the other neighbor may be decreased by the same delta voltage. In one aspect, programming of an upper page of data into a word line that neighbors a target word line is halted to allow lower page data in the target memory cells to be read using an IDL and preserved in data latches while programming the upper page in the neighbor word completes. Preservation of the lower page data provides for a cleaner lower page when later programming the upper page into the target memory cells.

Abstract: Techniques are disclosed herein for performing an Internal Data Load (IDL) to sense non-volatile storage elements. Read pass voltages that are applied to the two neighbor word lines to a selected word line may be adjusted to result in a more accurate IDL. The read pass voltage for one neighbor may be increased by some delta voltage, whereas the read pass voltage for the other neighbor may be decreased by the same delta voltage. In one aspect, programming of an upper page of data into a word line that neighbors a target word line is halted to allow lower page data in the target memory cells to be read using an IDL and preserved in data latches while programming the upper page in the neighbor word completes. Preservation of the lower page data provides for a cleaner lower page when later programming the upper page into the target memory cells.

Abstract: A system for reducing read disturb on edge word lines in non-volatile storage is disclosed. In one embodiment, the memory cells on edge word lines are programmed using a series of pulses that have an initial magnitude and step size between pulses that are lower than for memory cells on word lines that are not edge word lines. Additionally, when reading memory cells on word lines that are not edge word lines, the edge word lines receive a lower pass voltage than the default pass voltage applied to other unselected word lines. In another embodiment, the system applies a higher than normal bias on a neighboring word lines when reading memory cells on an edge word line.

Abstract: Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the word line that is selected for programming. Applying a selected word line dependent program condition may reduce or eliminate program disturb. The duration of a programming pulse may depend on the word line that is selected for programming. This could be a physical characteristic of the word line or its location on a NAND string. As one example, a shorter pulse width may be used for the programming signal when programming edge word lines.

Abstract: Techniques for efficiently programming non-volatile storage are disclosed. A second page of data may efficiently be programmed into memory cells that already store a first page. Data may be efficiently transferred from single bit cells to multi-bit cells. Memory cells are read using at least two different read levels. The results are compared to determine a count how many memory cells showed a different result between the two reads. If the count is less than a threshold, then data from the memory cells is stored into a set of data latches without attempting to correct for misreads. If the count is not less than the threshold, then data from the memory cells is stored into the set of data latches with attempting to correct for misreads. A programming operation may be performed based on the data stored in the set of data latches.

Abstract: Methods and devices for operating non-volatile storage are disclosed. One or more programming conditions depend on the word line that is selected for programming. Applying a selected word line dependent program condition may reduce or eliminate program disturb. The duration of a programming pulse may depend on the word line that is selected for programming. This could be a physical characteristic of the word line or its location on a NAND string. As one example, a shorter pulse width may be used for the programming signal when programming edge word lines.

Abstract: Methods, devices, and systems associated with multilevel phase change memory cells are described herein. One or more embodiments of the present disclosure include operating a phase change memory device by placing a phase change memory cell in a reset state and applying a selected programming pulse to the phase change memory cell in order to program the cell to one of a number of intermediate states between the reset state and a set state associated with the cell. The selected programming pulse includes an uppermost magnitude applied for a particular duration, the particular duration depending on to which one of the number of intermediate states the memory cell is to be programmed.