Abstract: Methods, devices, and systems associated with multilevel phase change memory cells are described herein. One or more embodiments of the present disclosure include operating a phase change memory device by placing a phase change memory cell in a reset state and applying a selected programming pulse to the phase change memory cell in order to program the cell to one of a number of intermediate states between the reset state and a set state associated with the cell. The selected programming pulse includes an uppermost magnitude applied for a particular duration, the particular duration depending on to which one of the number of intermediate states the memory cell is to be programmed.

Abstract: Methods, devices, and systems associated with multilevel phase change memory cells are described herein. One or more embodiments of the present disclosure include operating a phase change memory device by placing a phase change memory cell in a reset state and applying a selected programming pulse to the phase change memory cell in order to program the cell to one of a number of intermediate states between the reset state and a set state associated with the cell. The selected programming pulse includes an uppermost magnitude applied for a particular duration, the particular duration depending on to which one of the number of intermediate states the memory cell is to be programmed.

Abstract: Methods, devices, and systems associated with multilevel phase change memory cells are described herein. One or more embodiments of the present disclosure include operating a phase change memory device by placing a phase change memory cell in a reset state and applying a selected programming pulse to the phase change memory cell in order to program the cell to one of a number of intermediate states between the reset state and a set state associated with the cell. The selected programming pulse includes an uppermost magnitude applied for a particular duration, the particular duration depending on to which one of the number of intermediate states the memory cell is to be programmed.

Abstract: Methods, devices, and systems associated with multilevel phase change memory cells are described herein. One or more embodiments of the present disclosure include operating a phase change memory device by placing a phase change memory cell in a reset state and applying a selected programming pulse to the phase change memory cell in order to program the cell to one of a number of intermediate states between the reset state and a set state associated with the cell. The selected programming pulse includes an uppermost magnitude applied for a particular duration, the particular duration depending on to which one of the number of intermediate states the memory cell is to be programmed.