Patents by Inventor Werner A. Rausch
Werner A. Rausch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080233687Abstract: A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.Type: ApplicationFiled: June 4, 2008Publication date: September 25, 2008Applicant: International Business Machines CorporationInventors: Huajie Chen, Omer H. Dokumaci, Oleg G. Gluschenkov, Werner A. Rausch
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Publication number: 20080230840Abstract: A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.Type: ApplicationFiled: June 4, 2008Publication date: September 25, 2008Applicant: International Business Machines CorporationInventors: Huajie Chen, Omer H. Dokumaci, Oleg G. Gluschenkov, Werner A. Rausch
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Patent number: 7402870Abstract: A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.Type: GrantFiled: October 12, 2004Date of Patent: July 22, 2008Assignee: International Business Machines CorporationInventors: Huajie Chen, Omer H. Dokumaci, Oleg G. Gluschenkov, Werner A. Rausch
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Publication number: 20080096342Abstract: The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits, as well as methods for forming such CMOS circuits. More specifically, the present invention relates to CMOS circuits that contain passive elements, such as buried resistors, capacitors, diodes, inductors, attenuators, power dividers, and antennas, etc., which are characterized by an end contact resistance of less than 90 ohm-microns. Such a low end resistance can be achieved either by reducing the spacer widths of the passive elements to a range of from about 10 nm to about 30 nm, or by masking the passive elements during a pre-amorphization implantation step, so that the passive elements are essentially free of pre-amorphization implants.Type: ApplicationFiled: December 14, 2007Publication date: April 24, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher Sheraw, Alyssa Bonnoit, K. Muller, Werner Rausch
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Patent number: 7361959Abstract: The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits, as well as methods for forming such CMOS circuits. More specifically, the present invention relates to CMOS circuits that contain passive elements, such as buried resistors, capacitors, diodes, inductors, attenuators, power dividers, and antennas, etc., which are characterized by an end contact resistance of less than 90 ohm-microns. Such a low end resistance can be achieved either by reducing the spacer widths of the passive elements to a range of from about 10 nm to about 30 nm, or by masking the passive elements during a pre-amorphization implantation step, so that the passive elements are essentially free of pre-amorphization implants.Type: GrantFiled: November 28, 2005Date of Patent: April 22, 2008Assignee: International Business Machines CorporationInventors: Christopher D. Sheraw, Alyssa C. Bonnoit, K. Paul Muller, Werner Rausch
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Publication number: 20070252212Abstract: The present invention provides an improved CMOS diode structure with dual gate conductors. Specifically, a substrate comprising a first n-doped region and a second p-doped region is formed. A third region of either n-type or p-type conductivity is located between the first and second regions. A first gate conductor of n-type conductivity and a second gate conductor of p-type conductivity are located over the substrate and adjacent to the first and second regions, respectively. Further, the second gate conductor is spaced apart and isolated from the first gate conductor by a dielectric isolation structure. An accumulation region with an underlying depletion region can be formed in such a diode structure between the third region and the second or the first region, and such an accumulation region preferably has a width that is positively correlated with that of the second or the first gate conductor.Type: ApplicationFiled: April 26, 2006Publication date: November 1, 2007Applicant: International Business Machines CorporationInventors: David Onsongo, Werner Rausch, Haining Yang
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Publication number: 20070120195Abstract: The present invention relates to complementary metal-oxide-semiconductor (CMOS) circuits, as well as methods for forming such CMOS circuits. More specifically, the present invention relates to CMOS circuits that contain passive elements, such as buried resistors, capacitors, diodes, inductors, attenuators, power dividers, and antennas, etc., which are characterized by an end contact resistance of less than 90 ohm-microns. Such a low end resistance can be achieved either by reducing the spacer widths of the passive elements to a range of from about 10 nm to about 30 nm, or by masking the passive elements during a pre-amorphization implantation step, so that the passive elements are essentially free of pre-amorphization implants.Type: ApplicationFiled: November 28, 2005Publication date: May 31, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher Sheraw, Alyssa Bonnoit, K. Muller, Werner Rausch
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Publication number: 20070045749Abstract: A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a respective opening in a first mask. A cap is formed over each of the first conductivity type wells, and the first mask is removed. Sidewall spacers are formed on sidewalls of each of the first conductivity type wells. A plurality of second conductivity type wells are formed, each of the plurality of second conductivity type wells are formed between respective first conductivity type wells. A plurality of shallow trench isolations are formed between the first conductivity type wells and second conductive type wells. The plurality of first conductivity type wells are formed by a first selective epitaxial growth process, and the plurality of second conductivity type wells are formed by a second selective epitaxial growth process.Type: ApplicationFiled: October 23, 2006Publication date: March 1, 2007Inventors: Wilfried Haensch, Terence Hook, Louis Hsu, Rajiv Joshi, Werner Rausch
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Publication number: 20070037356Abstract: A method is provided for forming an SOI MOSFET device with a silicon layer formed on a dielectric layer with a gate electrode stack, with sidewall spacers on sidewalls of the gate electrode stack and raised source/drain regions formed on the surface of the silicon layer. The gate electrode stack comprises a gate electrode formed of polysilicon over a gate dielectric layer formed on the surface of the silicon layer. A thin amorphous silicon cap layer is formed in the top surface of the gate electrode by implanting dopant into the surface thereof. A notch is etched into the periphery of the cap layer. A plug of dielectric material is formed in the notch. The sidewalls of the gate electrode are covered by the sidewall spacers which cover a portion of the plug for the purpose of eliminating the exposure of the gate polysilicon so that formation of spurious epitaxial growth during the formation of raised source/drain regions is avoided.Type: ApplicationFiled: October 23, 2006Publication date: February 15, 2007Inventors: Tina Wagner, Werner Rausch, Sadanand Deshpande
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Patent number: 7176481Abstract: Disclosed is an integrated circuit structure and a method of making such a structure that has a substrate and P-type and N-type transistors on the substrate. The N-type transistor extension and source/drain regions comprise dopants implanted into the substrate. The P-type transistor extension and source/drain regions partially include a strained epitaxial silicon germanium, wherein the strained silicon germanium comprises of two layers, with a top layer that is closer to the gate stack than the bottom layer. The strained silicon germanium is in-situ doped and creates longitudinal stress on the channel region.Type: GrantFiled: January 12, 2005Date of Patent: February 13, 2007Assignee: International Business Machines CorporationInventors: Huajie Chen, Dureseti Chidambarrao, Siddhartha Panda, Sang-Hyun Oh, Henry K. Utomo, Werner A. Rausch
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Patent number: 7163866Abstract: Disadvantages of the floating body of a SOI MOSFET are addressed by providing a pocket halo implant of indium beneath the gate and in the channel region of the semiconductor SOI layer of the MOSFET. Also provided is the method for fabricating the device.Type: GrantFiled: December 11, 2003Date of Patent: January 16, 2007Assignee: International Business Machines CorporationInventors: Fariborz Assaderaghi, Werner Rausch, Dominic Joseph Schepis, Ghavam G. Shahidi
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Publication number: 20060292779Abstract: A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.Type: ApplicationFiled: August 10, 2006Publication date: December 28, 2006Applicants: International Business Machines Corporation, Toshiba America ElectronicInventors: Huajie Chen, Dureseti Chidambarrao, Sang-Hyun Oh, Siddhartha Panda, Werner Rausch, Tsutomu Sato, Henry Utomo
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Patent number: 7135724Abstract: A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.Type: GrantFiled: September 29, 2004Date of Patent: November 14, 2006Assignees: International Business Machines Corporation, Kabushiki Kaisha ToshibaInventors: Huajie Chen, Dureseti Chidambarrao, Sang-Hyun Oh, Siddhartha Panda, Werner A. Rausch, Tsutomu Sato, Henry K. Utomo
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Patent number: 7132323Abstract: A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a respective opening in a first mask. A cap is formed over each of the first conductivity type wells, and the first mask is removed. Sidewall spacers are formed on sidewalls of each of the first conductivity type wells. A plurality of second conductivity type wells are formed, each of the plurality of second conductivity type wells are formed between respective first conductivity type wells. A plurality of shallow trench isolations are formed between the first conductivity type wells and second conductive type wells. The plurality of first conductivity type wells are formed by a first selective epitaxial growth process, and the plurality of second conductivity type wells are formed by a second selective epitaxial growth process.Type: GrantFiled: November 14, 2003Date of Patent: November 7, 2006Assignee: International Business Machines CorporationInventors: Wilfried Haensch, Terence B. Hook, Louis C. Hsu, Rajiv V. Joshi, Werner Rausch
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Publication number: 20060151837Abstract: Disclosed is an integrated circuit structure and a method of making such a structure that has a substrate and P-type and N-type transistors on the substrate. The N-type transistor extension and source/drain regions comprise dopants implanted into the substrate. The P-type transistor extension and source/drain regions partially include a strained epitaxial silicon germanium, wherein the strained silicon germanium comprises of two layers, with a top layer that is closer to the gate stack than the bottom layer. The strained silicon germanium is in-situ doped and creates longitudinal stress on the channel region.Type: ApplicationFiled: January 12, 2005Publication date: July 13, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Huajie Chen, Dureseti Chidambarrao, Siddhartha Panda, Sang-Hyun Oh, Henry Utomo, Werner Rausch
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Patent number: 7071103Abstract: The present invention provides a method for retarding the diffusion of dopants from a first material layer (typically a semiconductor) into an overlayer or vice versa. In the method of the present invention, diffusion of dopants from the first semiconductor into the overlayer or vice versa is retarded by forming a monolayer comprising carbon and oxygen between the two layers. The monolayer is formed in the present invention utilizing a chemical pretreatment process in which a solution including iodine and an alcohol such as methanol is employed.Type: GrantFiled: July 30, 2004Date of Patent: July 4, 2006Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Huajie Chen, Michael A. Gribelyuk, Judson R. Holt, Woo-Hyeong Lee, Ryan M. Mitchell, Renee T. Mo, Dan M. Mocuta, Werner A. Rausch, Paul A. Ronsheim, Henry K. Utomo
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Publication number: 20060076627Abstract: A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.Type: ApplicationFiled: October 12, 2004Publication date: April 13, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Huajie Chen, Omer Dokumaci, Oleg Gluschenkov, Werner Rausch
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Publication number: 20060065914Abstract: A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.Type: ApplicationFiled: September 29, 2004Publication date: March 30, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Huajie Chen, Dureseti Chidambarrao, Sang-Hyun Oh, Siddhartha Panda, Werner Rausch, Tsutomu Sato, Henry Utomo
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Publication number: 20060024934Abstract: The present invention provides a method for retarding the diffusion of dopants from a first material layer (typically a semiconductor) into an overlayer or vice versa. In the method of the present invention, diffusion of dopants from the first semiconductor into the overlayer or vice versa is retarded by forming a monolayer comprising carbon and oxygen between the two layers. The monolayer is formed in the present invention utilizing a chemical pretreatment process in which a solution including iodine and an alcohol such as methanol is employed.Type: ApplicationFiled: July 30, 2004Publication date: February 2, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin Chan, Huajie Chen, Michael Gribelyuk, Judson Holt, Woo-Hyeong Lee, Ryan Mitchell, Renee Mo, Dan Mocuta, Werner Rausch, Paul Ronsheim, Henry Utomo
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Patent number: 6939751Abstract: An RSD FET device with a recessed channel is formed with a raised silicon sources and drains and a gate electrode structure formed on an SOI structure (a Si layer formed on a substrate) by the steps as follows. Form a SiGe layer over the Si layer and a RSD layer over the SiGe. Etch through the RSD layer and the SiGe to form a gate electrode space reaching down the Si layer. Form a pair of RSD regions separated by the gate electrode space. Line the walls of the gate electrode space with an internal etch stop layer and an inner sidewall spacers. Form a gate electrode inside the inner sidewall spacers on the Si layer. Form external sidewall spacers adjacent to the gate electrode between the RSD regions next to the inner sidewall spacers, and dope the RSD regions, whereby a recessed channel is formed in the SOI silicon layer between the raised source/drain regions thereabove and below the level of the SiGe layer.Type: GrantFiled: October 22, 2003Date of Patent: September 6, 2005Assignee: International Business Machines CorporationInventors: Huilong Zhu, Bruce B. Doris, Werner A. Rausch, Ying Zhang